
Zig Cross
- 310 installs
- 155 repo stars
- Updated June 27, 2026
- mohitmishra786/low-level-dev-skills
Configure Zig cross-compilation for alternate OS/arch targets, validate artifacts, and ship portable binaries without native toolchains on each platform.
About
Teaches Zig cross-compilation from low-level-dev-skills: selecting targets, managing sysroots and linkers, building for Linux/macOS/Windows/arm from one host, and validating shipped native binaries across platforms.
- Target triple selection
- Cross libc and linker setup
- Multi-arch release builds
- Artifact smoke checks
- CI-friendly portable binaries
Zig Cross by the numbers
- 310 all-time installs (skills.sh)
- +21 installs in the week ending Aug 4, 2026 (Skillselion tracking)
- Ranked #171 of 550 CLI & Terminal skills by installs in the Skillselion catalog
- Data as of Aug 4, 2026 (Skillselion catalog sync)
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| Installs | 310 |
|---|---|
| repo stars | ★ 155 |
| Last updated | June 27, 2026 |
| Repository | mohitmishra786/low-level-dev-skills ↗ |
What it does
Configure Zig cross-compilation for alternate OS/arch targets, validate artifacts, and ship portable binaries without native toolchains on each platform.
Files
Zig Cross-Compilation
Purpose
Guide agents through Zig's built-in cross-compilation: target triple selection, CPU feature targeting, zig cc for cross-compiling C projects, embedded bare-metal targets, and WASM output — all without requiring a system cross-toolchain.
Triggers
- "How do I cross-compile a Zig program for ARM?"
- "How do I build Zig for a different OS?"
- "How do I use Zig to cross-compile C code for another platform?"
- "How do I build Zig for embedded/bare-metal?"
- "How do I target WebAssembly with Zig?"
- "What Zig target triple do I use for Raspberry Pi?"
Workflow
1. Zig's native cross-compilation
Zig has cross-compilation built in — no cross-toolchain, no Docker, no sysroot needed for pure Zig code:
# List all supported targets
zig targets | python3 -c "import sys,json; d=json.load(sys.stdin); [print(t) for t in d['libc']]"
# Build for a specific target
zig build-exe src/main.zig -target aarch64-linux-gnu -O ReleaseFast
# With build system (pass target as option)
zig build -Dtarget=aarch64-linux-gnu -Doptimize=ReleaseFast
# Cross-compile for Windows from Linux/macOS
zig build-exe src/main.zig -target x86_64-windows-gnu
# Cross-compile for macOS from Linux (requires macOS SDK)
zig build-exe src/main.zig -target aarch64-macos-none2. Common target triples
| Target triple | Platform |
|---|---|
x86_64-linux-gnu | Linux x86-64 (glibc) |
x86_64-linux-musl | Linux x86-64 (musl, static) |
aarch64-linux-gnu | ARM64 Linux (Pi 4, AWS Graviton) |
aarch64-linux-musl | ARM64 Linux static |
armv7-linux-gnueabihf | ARM 32-bit Linux (Pi 2/3) |
x86_64-windows-gnu | Windows x86-64 |
aarch64-macos-none | macOS Apple Silicon |
x86_64-macos-none | macOS Intel |
wasm32-freestanding | WASM (browser, no OS) |
wasm32-wasi | WASM with WASI |
thumbv7m-freestanding-eabi | Cortex-M3 bare metal |
thumbv7em-freestanding-eabihf | Cortex-M4/M7 with FPU |
riscv32-freestanding | RISC-V 32-bit bare metal |
3. CPU feature targeting
# Native CPU (auto-detect, only for native builds)
zig build-exe src/main.zig -mcpu native
# Baseline for architecture (most compatible)
zig build-exe src/main.zig -target x86_64-linux-gnu -mcpu baseline
# x86-64 with AVX2
zig build-exe src/main.zig -target x86_64-linux-gnu -mcpu x86_64+avx2+bmi2
# Raspberry Pi 4 (Cortex-A72)
zig build-exe src/main.zig -target aarch64-linux-gnu -mcpu cortex_a72
# Cortex-M4 with FPU
zig build-exe src/main.zig \
-target thumbv7em-freestanding-eabihf \
-mcpu cortex_m4+vfp4
# List CPU features for a target
zig targets | python3 -c "
import sys,json
d=json.load(sys.stdin)
for c in d['cpus']:
if 'cortex' in c['name']:
print(c['name'])
"4. zig cc for C cross-compilation
zig cc cross-compiles C without a system cross-toolchain:
# Cross-compile C for ARM64 Linux
zig cc -target aarch64-linux-gnu -O2 -o myapp-arm64 main.c
# Cross-compile C for Windows
zig cc -target x86_64-windows-gnu main.c -o myapp.exe
# Cross-compile C with static musl linking
zig cc -target x86_64-linux-musl -static main.c -o myapp-static
# Use in Makefile for all platforms
CC_LINUX_AMD64 = zig cc -target x86_64-linux-gnu
CC_LINUX_ARM64 = zig cc -target aarch64-linux-gnu
CC_WINDOWS = zig cc -target x86_64-windows-gnu5. Build system cross-compilation
// build.zig — cross-build all targets
pub fn build(b: *std.Build) void {
const targets = [_]std.Target.Query{
.{ .cpu_arch = .x86_64, .os_tag = .linux, .abi = .gnu },
.{ .cpu_arch = .aarch64, .os_tag = .linux, .abi = .gnu },
.{ .cpu_arch = .x86_64, .os_tag = .windows, .abi = .gnu },
.{ .cpu_arch = .aarch64, .os_tag = .macos },
};
for (targets) |t| {
const target = b.resolveTargetQuery(t);
const exe = b.addExecutable(.{
.name = b.fmt("myapp-{s}", .{@tagName(t.cpu_arch.?)}),
.root_source_file = b.path("src/main.zig"),
.target = target,
.optimize = .ReleaseFast,
});
b.installArtifact(exe);
}
}# Build all targets
zig build
# Creates: zig-out/bin/myapp-x86_64, myapp-aarch64, myapp-x86_64.exe, myapp-aarch646. Embedded (bare-metal) targets
# Cortex-M4 with FPU (STM32F4xx)
zig build-exe src/main.zig \
-target thumbv7em-freestanding-eabihf \
-mcpu cortex_m4+vfp4 \
-O ReleaseSmall \
--script linker.ld// src/main.zig — bare metal entry point
const std = @import("std");
// Custom panic handler for embedded (no OS)
pub fn panic(msg: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
// Toggle LED or halt
while (true) {}
}
// Entry point (matches linker script)
export fn _start() void {
main() catch |err| {
_ = err;
while (true) {}
};
}
fn main() !void {
// Hardware initialization...
}7. WebAssembly
# WASM freestanding (browser)
zig build-exe src/main.zig \
-target wasm32-freestanding \
-O ReleaseSmall \
--export=init \
--export=update \
-fno-entry
# WASM WASI (wasmtime, wasmer)
zig build-exe src/main.zig \
-target wasm32-wasi \
-O ReleaseSafe
wasmtime myapp.wasm
# Optimize WASM size
wasm-opt -Oz myapp.wasm -o myapp.opt.wasmFor target triple reference and embedded linker script setup, see references/zig-target-triples.md.
Related skills
- Use
skills/zig/zig-compilerfor single-file compilation flags - Use
skills/zig/zig-build-systemfor multi-target build.zig configuration - Use
skills/compilers/cross-gccfor system cross-toolchain setup when needed - Use
skills/rust/rust-crossfor Rust's cross-compilation approach comparison
Zig Target Triples Reference
Triple Format
<cpu_arch>-<os>-<abi>cpu_arch: x86_64, aarch64, arm, thumb, thumbv6m, thumbv7m, thumbv7em, thumbv8m, riscv32, riscv64, mips, mipsel, wasm32, wasm64, ...os: linux, windows, macos, ios, freebsd, netbsd, openbsd, dragonfly, solaris, freestanding, wasi, otherabi: none, gnu, gnueabi, gnueabihf, musl, musleabi, musleabihf, eabi, eabihf, msvc, android, ...
Linux Targets
| Triple | ABI | Notes |
|---|---|---|
x86_64-linux-gnu | glibc | Standard Linux x86-64 |
x86_64-linux-musl | musl | Static, no glibc dep |
x86_64-linux-gnux32 | glibc x32 | 32-bit pointers on 64-bit |
aarch64-linux-gnu | glibc | ARM64 Linux |
aarch64-linux-musl | musl | ARM64 static |
aarch64_be-linux-gnu | glibc | ARM64 big-endian |
arm-linux-gnueabi | glibc soft-float | ARM32, no FPU |
arm-linux-gnueabihf | glibc hard-float | ARM32 with FPU |
armv7-linux-gnueabihf | glibc | ARMv7 with FPU (Pi 2/3) |
riscv32-linux-gnu | glibc | RISC-V 32-bit Linux |
riscv64-linux-gnu | glibc | RISC-V 64-bit Linux |
mipsel-linux-gnu | glibc | MIPS little-endian |
powerpc64le-linux-gnu | glibc | POWER little-endian |
s390x-linux-gnu | glibc | IBM Z Series |
Windows Targets
| Triple | Notes |
|---|---|
x86_64-windows-gnu | MinGW ABI, cross-compilable |
x86_64-windows-msvc | MSVC ABI, requires Windows SDK |
aarch64-windows-gnu | ARM64 Windows (MinGW) |
i386-windows-gnu | 32-bit Windows |
macOS / iOS Targets
| Triple | Notes |
|---|---|
x86_64-macos-none | macOS Intel |
aarch64-macos-none | macOS Apple Silicon (M1/M2/M3) |
x86_64-ios-none | iOS Simulator (x86-64) |
aarch64-ios-none | iOS device |
Note: Cross-compiling to macOS requires the macOS SDK.
Embedded (Freestanding) Targets
ARM Cortex-M
| Triple | MCU Family | Notes |
|---|---|---|
thumb-freestanding-eabi | Generic Thumb | |
thumbv6m-freestanding-eabi | Cortex-M0/M0+ | RP2040 core |
thumbv7m-freestanding-eabi | Cortex-M3 | STM32F1, LPC17xx |
thumbv7em-freestanding-eabi | Cortex-M4/M7 (soft-float) | |
thumbv7em-freestanding-eabihf | Cortex-M4/M7 (hard-float) | STM32F4/F7, nRF52 |
thumbv8m.base-freestanding-eabi | Cortex-M23 | |
thumbv8m.main-freestanding-eabi | Cortex-M33/M35P | STM32U5, nRF9160 |
thumbv8m.main-freestanding-eabihf | Cortex-M33 with FPU |
ARM Cortex-A (freestanding)
| Triple | CPU | Use case |
|---|---|---|
aarch64-freestanding-eabi | Cortex-A (64-bit) | Bare-metal A72 |
arm-freestanding-eabihf | Cortex-A (32-bit) | Bare-metal A9/A15 |
RISC-V
| Triple | Notes |
|---|---|
riscv32-freestanding | RISC-V 32-bit (generic) |
riscv32im-freestanding | With multiply extension |
riscv32imc-freestanding | With multiply and compressed |
riscv32imac-freestanding | With atomics (ESP32-C3) |
riscv64-freestanding | RISC-V 64-bit |
riscv64gc-freestanding | RISC-V 64 with GC extensions |
Other
| Triple | Notes |
|---|---|
mips-freestanding-none | MIPS32 bare metal |
avr-freestanding-none | AVR (Arduino) |
bpf-freestanding-none | eBPF |
WASM Targets
| Triple | Use case |
|---|---|
wasm32-freestanding | Browser (no WASI) |
wasm32-wasi | WASI runtime (wasmtime/wasmer) |
wasm64-freestanding | 64-bit WASM (experimental) |
CPU Feature Strings
# x86_64 common features
x86_64 # baseline (SSE2 only)
x86_64+sse4.2 # SSE 4.2
x86_64+avx # AVX (Sandy Bridge)
x86_64+avx2+bmi+bmi2 # AVX2 (Haswell)
x86_64+avx512f # AVX-512 Foundation
x86_64v2 # x86-64-v2 microarch level
x86_64v3 # x86-64-v3 (AVX2, BMI2)
# ARM64 common CPUs
cortex_a53 # Pi 3, many phones
cortex_a72 # Pi 4
cortex_a76 # Snapdragon 855+
apple_m1 # Apple M1
neoverse_n1 # AWS Graviton2
# ARM Cortex-M CPUs
cortex_m0 # Cortex-M0
cortex_m0plus # Cortex-M0+
cortex_m3 # Cortex-M3
cortex_m4 # Cortex-M4 (no FPU)
cortex_m4+vfp4 # Cortex-M4 with FPU
cortex_m7+vfp5_d16 # Cortex-M7 with FPU
cortex_m33 # Cortex-M33
cortex_m33+vfp5_d16 # Cortex-M33 with FPU
# RISC-V extensions
riscv32i # Base integer
riscv32im # + Multiply
riscv32imc # + Compressed
riscv32imac # + Atomics + Compressed
riscv64gc # 64-bit general