Esp32 Firmware Engineer
Write, review, and debug ESP-IDF firmware on ESP32 variants with FreeRTOS, drivers, OTA, sleep modes, and security hardening.
Overview
ESP32 Firmware Engineer is an agent skill most often used in Build (also Ship, Operate) that writes, reviews, and debugs ESP-IDF firmware with OTA, power, and security hardening.
Install
npx skills add https://github.com/adamlipecz/esp32-firmware-engineer-skill --skill esp32-firmware-engineerWhat is this skill?
- Covers ESP-IDF C/C++ write, review, and debug across esp32, S3, C3, C6, and related variants
- Diagnoses Guru Meditation panics, reset reasons, boot failures, and FreeRTOS race conditions
- Designs OTA partition tables and implements secure boot, flash encryption, and NVS encryption
- Implements I2C, SPI, UART, TWAI/CAN, ADC, PWM, GPIO, RMT, LVGL, and ESP-ADF/ESP-SR integration
- Optimizes RAM, flash, and code size plus deep/light sleep with correct wakeup sources
Adoption & trust: 591 installs on skills.sh; 5 GitHub stars; 2/3 security scanners passed (skills.sh audits).
What problem does it solve?
Your ESP32 project hits opaque panics, fragile tasks, or misconfigured partitions and you lack a consistent ESP-IDF workflow for bring-up, drivers, and production updates.
Who is it for?
Solo builders and small teams shipping ESP-IDF products who need end-to-end firmware guidance from build through OTA and field diagnostics.
Skip if: Pure Arduino-only sketches with no IDF toolchain, or hosts where no serial flash/monitor workflow is available.
When should I use this skill?
User mentions ESP32, ESP-IDF, idf.py, FreeRTOS on Espressif, OTA partitions, Guru Meditation, sdkconfig, or embedded drivers.
What do I get? / Deliverables
You get actionable firmware changes, validated driver and sleep configurations, and clearer OTA and security setup aligned with your exact chip and IDF version.
- Reviewed or patched firmware source and sdkconfig guidance
- OTA partition and security configuration recommendations
- Panic and reset diagnosis steps with remediation
Recommended Skills
Journey fit
Spans multiple journey phases - primary shelf plus alternate fits below.
Primary work is implementing and integrating on-device firmware, which maps to Build even though OTA and ops topics appear later in the journey. Firmware, drivers, partitions, and IDF build flows are embedded backend engineering rather than frontend or pure DevOps scripts.
Where it fits
Bring up I2C sensor driver and task priorities on ESP32-C6 with correct sdkconfig defaults.
Integrate LVGL with a display controller and validate frame timing under ESP-IDF.
Enable Secure Boot v2 and flash encryption before signing an OTA-capable release image.
Parse reset reason and Guru Meditation backtrace after an ISR-related crash in production logs.
How it compares
Embedded firmware workflow skill for ESP-IDF, not a cloud IaC or mobile app UI kit.
Common Questions / FAQ
Who is esp32-firmware-engineer for?
Indie hardware and firmware developers using ESP-IDF on ESP32-family chips who want agent help for drivers, RTOS, OTA, and security.
When should I use esp32-firmware-engineer?
In Build for new firmware and peripherals; in Ship for OTA partition design and secure boot; in Operate when decoding panics, reset reasons, or power regressions in the field.
Is esp32-firmware-engineer safe to install?
It instructs flash, monitor, and security configuration—review the Security Audits panel on this Prism page and treat production keys and signing material as secrets you control locally.
SKILL.md
READMESKILL.md - Esp32 Firmware Engineer
interface: display_name: "ESP32 Firmware Engineer" short_description: "ESP-IDF firmware write, review, debug, power, OTA, security, and bring-up" # Claude Code skill invocation: @esp32-firmware-engineer or via SKILL.md trigger matching activation_keywords: - esp32 - esp-idf - esp32s3 - esp32c3 - esp32c6 - esp32s2 - freertos - idf.py - guru meditation - sdkconfig - partitions.csv - esp-adf - esp-sr - lvgl - deep sleep - light sleep - secure boot - flash encryption capabilities: - Write, review, and debug ESP-IDF C/C++ firmware - Analyze FreeRTOS task/queue/semaphore/ISR patterns and race conditions - Diagnose Guru Meditation panics, reset reasons, and boot failures - Optimize RAM, flash, and code size - Design OTA-compatible partition tables and implement OTA update flows - Configure deep sleep and light sleep power modes with correct wakeup sources - Implement I2C, SPI, UART, TWAI/CAN, ADC, PWM, GPIO, and RMT drivers - Integrate and validate LVGL with ESP-IDF and display controllers - Add on-device USB/serial service terminals with runtime diagnostics - Validate ESP-ADF/ESP-SR plugin compatibility (online and local) - Harden firmware with Secure Boot v2, flash encryption, NVS encryption - Fix build, flash, and monitor workflow issues required_context: - Exact ESP32 variant (esp32, esp32s3, esp32c3, esp32c6, etc.) - ESP-IDF version - Board pinmap and hardware constraints - Relevant sdkconfig settings and flash size model_hints: prefer_extended_thinking: true # deep bug triage and architectural decisions benefit from it tool_use: true context_window: large # reference docs are read in full during triage default_prompt: | Use the esp32-firmware-engineer skill to implement, review, or debug this ESP-IDF task. Block on missing context: require exact ESP32 variant, ESP-IDF version, and hardware details (pin map, peripheral list, flash size) before proceeding with hardware-integrated work. Load SKILL.md plus the minimum relevant references before writing any code. interface: display_name: "ESP32 Firmware Engineer" short_description: "ESP-IDF firmware write, review, debug, power, OTA, security, and bring-up" activation_keywords: - esp32 - esp-idf - esp32s3 - esp32c3 - esp32c6 - esp32s2 - freertos - idf.py - guru meditation - sdkconfig - partitions.csv - esp-adf - esp-sr - lvgl - deep sleep - light sleep - secure boot - flash encryption capabilities: - Write, review, and debug ESP-IDF C/C++ firmware - Analyze FreeRTOS task/queue/semaphore/ISR patterns and race conditions - Diagnose Guru Meditation panics, reset reasons, and boot failures - Optimize RAM, flash, and code size - Design OTA-compatible partition tables and implement OTA update flows - Configure deep sleep and light sleep power modes with correct wakeup sources - Implement I2C, SPI, UART, TWAI/CAN, ADC, PWM, GPIO, and RMT drivers - Integrate and validate LVGL with ESP-IDF and display controllers - Add on-device USB/serial service terminals with runtime diagnostics - Validate ESP-ADF/ESP-SR plugin compatibility (online and local) - Harden firmware with Secure Boot v2, flash encryption, NVS encryption - Fix build, flash, and monitor workflow issues required_context: - Exact ESP32 variant (esp32, esp32s3, esp32c3, esp32c6, etc.) - ESP-IDF version - Board pinmap and hardware constraints - Relevant sdkconfig settings and flash size default_prompt: | Use the esp32-firmware-engineer skill to implement, review, or debug this ESP-IDF task. Block on missing context: require exact ESP32 variant, ESP-IDF version, and hardware details (pin map, peripheral list, flash size) before proceeding with hardware-integrated work. # ESP framework