Assembly Arm

ARM / AArch64 Assembly

Purpose

Guide agents through AArch64 (64-bit) and ARM (32-bit Thumb) assembly: registers, calling conventions, inline asm, and NEON/SVE SIMD patterns.

Triggers

• "How do I read ARM64 assembly output?"
• "What are the AArch64 registers and calling convention?"
• "How do I write inline asm for ARM?"
• "What is the difference between AArch64 and ARM Thumb?"
• "How do I use NEON intrinsics?"

Workflow

1. Generate ARM assembly

# AArch64 (native or cross-compile)
aarch64-linux-gnu-gcc -S -O2 foo.c -o foo.s

# 32-bit ARM Thumb
arm-linux-gnueabihf-gcc -S -O2 -mthumb foo.c -o foo.s

# From objdump
aarch64-linux-gnu-objdump -d -S prog

# From GDB on target
(gdb) disassemble /s main

2. AArch64 registers (AAPCS64)

Width variants: x0 (64-bit), w0 (32-bit, zero-extends to 64), h0 (16), b0 (8).

3. AAPCS64 calling convention

Integer/pointer args: x0–x7 Float/SIMD args: v0–v7 Return: x0 (int), x0+x1 (128-bit), v0 (float/SIMD) Callee-saved: x19–x28, x29 (fp), x30 (lr), v8–v15 (lower 64 bits) Caller-saved: everything else

Stack must be 16-byte aligned at any bl or blr instruction.

4. Common AArch64 instructions

5. Typical function prologue/epilogue

// Non-leaf function
stp  x29, x30, [sp, #-32]!   // save fp, lr; allocate 32 bytes
mov  x29, sp                  // set frame pointer
stp  x19, x20, [sp, #16]     // save callee-saved registers
// ... body ...
ldp  x19, x20, [sp, #16]     // restore
ldp  x29, x30, [sp], #32     // restore fp, lr; deallocate
ret

// Leaf function (no calls, no callee-saved regs needed)
// Can use red zone (no rsp adjustment) — but AArch64 has no red zone
sub  sp, sp, #16             // allocate locals
// ... body ...
add  sp, sp, #16
ret

6. Inline assembly (GCC/Clang)

// Barrier
__asm__ volatile ("dmb ish" ::: "memory");

// Load acquire
static inline int load_acquire(volatile int *p) {
    int val;
    __asm__ volatile ("ldar %w0, %1" : "=r"(val) : "Q"(*p));
    return val;
}

// Store release
static inline void store_release(volatile int *p, int val) {
    __asm__ volatile ("stlr %w1, %0" : "=Q"(*p) : "r"(val));
}

// Read system counter
static inline uint64_t read_cntvct(void) {
    uint64_t val;
    __asm__ volatile ("mrs %0, cntvct_el0" : "=r"(val));
    return val;
}

AArch64-specific constraints:

• "Q" — memory operand suitable for exclusive/acquire/release instructions
• "r" — any general-purpose register
• "w" — any FP/SIMD register

7. NEON SIMD intrinsics

#include <arm_neon.h>

// Add 4 floats at once
float32x4_t a = vld1q_f32(arr_a);   // load 4 floats
float32x4_t b = vld1q_f32(arr_b);
float32x4_t c = vaddq_f32(a, b);
vst1q_f32(result, c);

// Horizontal sum
float32x4_t sum = vpaddq_f32(c, c);
sum = vpaddq_f32(sum, sum);
float total = vgetq_lane_f32(sum, 0);

Naming convention: v<op><q>_<type>

• q suffix: 128-bit (quad) vector
• _f32: float32, _s32: int32, _u8: uint8, etc.

For a register reference, see references/reference.md.

Related skills

• Use skills/low-level-programming/assembly-x86 for x86-64 assembly
• Use skills/compilers/cross-gcc for cross-compilation toolchain
• Use skills/debuggers/gdb for debugging ARM code with gdbserver

AArch64 / ARM Assembly Reference

Source: <https://developer.arm.com/documentation/ddi0487/latest> (ARM Architecture Reference Manual) Source: <https://developer.arm.com/documentation/ihi0055/latest> (AAPCS64)

Table of Contents

1. Condition codes 2. Key instructions by category 3. Memory ordering 4. NEON data types 5. Thumb-2 notes

---

Condition codes

Conditional branches: b.eq, b.ne, b.lt, b.ge, b.hi, b.ls, etc.

---

Key instructions by category

Loads and stores

ldr  x0, [x1]           ; load 64-bit
ldr  w0, [x1]           ; load 32-bit, zero-extend
ldrb w0, [x1]           ; load 8-bit, zero-extend
ldrsb w0, [x1]          ; load 8-bit, sign-extend
ldrh w0, [x1]           ; load 16-bit, zero-extend

str  x0, [x1]           ; store 64-bit
strb w0, [x1]           ; store byte

; Pre-index: update base before access
ldr  x0, [x1, #8]!     ; x0 = [x1+8]; x1 += 8

; Post-index: update base after access
ldr  x0, [x1], #8      ; x0 = [x1]; x1 += 8

; Pair operations
ldp  x0, x1, [x2]      ; load pair
stp  x0, x1, [x2, #-16]!  ; store pair, pre-decrement

; Exclusive access (for atomics)
ldxr x0, [x1]          ; load exclusive
stxr w2, x0, [x1]      ; store exclusive; w2=0 on success

; Acquire/release (for lock-free)
ldar  x0, [x1]         ; load-acquire
stlr  x0, [x1]         ; store-release

Arithmetic and logic

add  x0, x1, x2         ; x0 = x1 + x2
add  x0, x1, x2, lsl #2 ; x0 = x1 + (x2 << 2)
adds x0, x1, x2          ; add, set flags
adc  x0, x1, x2          ; add with carry

sub  x0, x1, x2
subs x0, x1, x2          ; sub, set flags
sbc  x0, x1, x2          ; sub with carry

mul   x0, x1, x2
madd  x0, x1, x2, x3    ; x0 = x1*x2 + x3
msub  x0, x1, x2, x3    ; x0 = x3 - x1*x2

and  x0, x1, x2
orr  x0, x1, x2
eor  x0, x1, x2         ; XOR
bic  x0, x1, x2         ; x0 = x1 & ~x2

lsl  x0, x1, #3         ; logical shift left 3
lsr  x0, x1, #3         ; logical shift right 3
asr  x0, x1, #3         ; arithmetic shift right 3
ror  x0, x1, #3         ; rotate right

clz  x0, x1             ; count leading zeros
rbit x0, x1             ; reverse bits
rev  x0, x1             ; reverse bytes (endian swap 64-bit)

Branches and system

b    label              ; unconditional branch
bl   label              ; branch and link (call)
blr  x0                 ; branch and link to register (indirect call)
br   x0                 ; branch to register (indirect jump)
ret                     ; return (branch to x30)

cbz  x0, label          ; branch if x0 == 0
cbnz x0, label          ; branch if x0 != 0
tbz  x0, #3, label      ; branch if bit 3 of x0 == 0
tbnz x0, #3, label      ; branch if bit 3 != 0

nop                     ; no operation
wfe                     ; wait for event
wfi                     ; wait for interrupt
isb                     ; instruction sync barrier
dsb  sy                 ; data sync barrier
dmb  ish                ; data memory barrier (inner shareable)

mrs  x0, cntvct_el0     ; read virtual timer count
mrs  x0, nzcv           ; read flags register
msr  nzcv, x0           ; write flags register

---

Memory ordering

---

NEON data types

Common intrinsic categories (prefix v):

• Load: vld1q_f32, vld2q_u8 (interleaved)
• Store: vst1q_f32
• Arithmetic: vaddq_f32, vsubq_s32, vmulq_f32
• Comparison: vcgeq_f32, vceqq_u8
• Shift: vshlq_n_u32, vshrq_n_s16
• Reorder: vuzpq_u8, vzipq_u8, vtrn1q_u32
• Horizontal: vpaddq_s32, vaddvq_f32

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Thumb-2 notes

32-bit ARM with Thumb-2 ISA (Cortex-M, Cortex-A in Thumb state):

• Most 32-bit ARM instructions available as Thumb-2 (32-bit encoding)
• Compact 16-bit encodings for common ops
• it (If-Then) block for conditional execution without branches
• No condition codes on most instructions by default; use s suffix to update flags
• bl range: ±16 MB; use blx for ARM↔Thumb interworking