Legacy Circuit Mockups

Legacy Circuit Mockups

A skill for creating breadboard circuit mockups and visual diagrams for retro computing and electronics projects. This skill leverages HTML5 Canvas drawing mechanisms to render interactive circuit layouts featuring vintage components like the 6502 microprocessor, 555 timer ICs, EEPROMs, and 7400-series logic gates.

• Leverage native parallel subagent dispatch and 200k+ context windows where available.

When to Use This Skill

Use symptom -> action triggers: when one matches, apply this skill and verify with the protocol below.

• User asks to create a breadboard layout or circuit mockup
• User wants visualized component placement for legacy electronics
• User needs diagrams for 6502, 555 timer, EEPROM, VIA, or 7400-series builds
• User asks for educational electronics visuals or wiring diagrams
• User is following retro-computing tutorials and needs visual references

Prerequisites

• Understanding of component pinouts from bundled reference files
• Knowledge of breadboard layout conventions (rows, columns, power rails)

Supported Components

Microprocessors & Memory

Logic & Timer ICs

Passive & Active Components

Grid System

// Standard breadboard grid: 20px spacing
const gridSize = 20;
const cellX = Math.floor(x / gridSize) * gridSize;
const cellY = Math.floor(y / gridSize) * gridSize;

Component Rendering Pattern

// All components follow this structure:
{
  type: 'component-type',
  x: gridX,
  y: gridY,
  width: componentWidth,
  height: componentHeight,
  rotation: 0,  // 0, 90, 180, 270
  properties: { /* component-specific data */ }
}

Wire Connections

// Wire connection format:
{
  start: { x: startX, y: startY },
  end: { x: endX, y: endY },
  color: '#ff0000'  // Wire color coding
}

Step-by-Step Workflows

Creating a Basic LED Circuit Mockup

1. Define breadboard dimensions and grid 2. Place power rail connections (+5V and GND) 3. Add LED component with anode/cathode orientation 4. Place current-limiting resistor 5. Draw wire connections between components 6. Add labels and annotations

Creating a 555 Timer Circuit

1. Place NE555 IC on breadboard (pins 1-4 left, 5-8 right) 2. Connect pin 1 (GND) to ground rail 3. Connect pin 8 (Vcc) to power rail 4. Add timing resistors and capacitors 5. Wire trigger and threshold connections 6. Connect output to LED or other load

Creating a 6502 Microprocessor Layout

1. Place W65C02S centered on breadboard 2. Add 28C256 EEPROM for program storage 3. Place W65C22 VIA for I/O 4. Add 7400-series logic for address decoding 5. Wire address bus (A0-A15) 6. Wire data bus (D0-D7) 7. Connect control signals (R/W, PHI2, RESB) 8. Add reset button and clock crystal

Component Pinout Quick Reference

555 Timer (8-pin DIP)

W65C02S (40-pin DIP) - Key Pins

28C256 EEPROM (28-pin DIP) - Key Pins

Formulas Reference

Resistor Calculations

• Ohm's Law: V = I × R
• LED Current: R = (Vcc - Vled) / Iled
• Power: P = V × I = I² × R

555 Timer Formulas

Astable Mode:

• Frequency: f = 1.44 / ((R1 + 2×R2) × C)
• High time: t₁ = 0.693 × (R1 + R2) × C
• Low time: t₂ = 0.693 × R2 × C
• Duty cycle: D = (R1 + R2) / (R1 + 2×R2) × 100%

Monostable Mode:

• Pulse width: T = 1.1 × R × C

Capacitor Calculations

• Capacitive reactance: Xc = 1 / (2πfC)
• Energy stored: E = ½ × C × V²

Color Coding Conventions

Wire Colors

LED Colors

Anti-Patterns

• Starting from a generic template without adapting it: The output may look polished but still miss the real audience or medium.
• Ignoring final render or export review: Layout bugs often appear only after the asset is opened in its destination tool.
• Fixing content and presentation in one pass: It becomes hard to tell whether a problem is structural or visual.

Verification Protocol

Before claiming "skill applied successfully":

1. Pass/fail: The Legacy Circuit Mockups implementation names the target runtime, framework version, and affected files. 2. Pass/fail: Build, lint, test, or equivalent local validation is run for the changed surface. 3. Pass/fail: Edge cases for errors, dependency drift, and environment differences are addressed or explicitly out of scope. 4. Pressure-test scenario: Apply the workflow to a change that passes happy-path tests but fails one boundary condition. 5. Success metric: Zero untested success claims; every implementation claim maps to a command or artifact.

Build Examples

Build 1 — Single LED

Components: Red LED, 220Ω resistor, jumper wires, power source

Steps:

1. Insert black jumper wire from power GND to row A5 2. Insert red jumper wire from power +5V to row J5 3. Place LED with cathode (short leg) in row aligned with GND 4. Place 220Ω resistor between power and LED anode

Build 2 — 555 Astable Blinker

Components: NE555, LED, resistors (10kΩ, 100kΩ), capacitor (10µF)

Steps:

1. Place 555 IC straddling center channel 2. Connect pin 1 to GND, pin 8 to +5V 3. Connect pin 4 to pin 8 (disable reset) 4. Wire 10kΩ between pin 7 and +5V 5. Wire 100kΩ between pins 6 and 7 6. Wire 10µF between pin 6 and GND 7. Connect pin 3 (output) to LED circuit

Troubleshooting

References

Detailed component specifications are available in the bundled reference files:

Documentation

• 555 — Complete 555 timer IC specification
• 6502 — MOS 6502 microprocessor details
• 6522 — W65C22 VIA interface adapter
• 28256-eeprom — AT28C256 EEPROM specification
• 6C62256 — 62256 SRAM details
• 7400-series — TTL logic gate pinouts
• assembly-compiler — Assembly compiler specification
• assembly-language — Assembly language specification
• basic-electronic-components — Resistors, capacitors, switches
• breadboard — Breadboard specifications
• common-breadboard-components — Comprehensive component reference
• connecting-electronic-components — Step-by-step build guides
• emulator-28256-eeprom — Emulating 28256-eeprom specification
• emulator-6502 — Emulating 6502 specification
• emulator-6522 — Emulating 6522 specification
• emulator-6C62256 — Emulating 6C62256 specification
• emulator-lcd — Emulating a LCD specification
• lcd — LCD display interfacing
• minipro — EEPROM programmer usage
• t48eeprom-programmer — T48 programmer reference

Examples

• Circuit Build Examples — Example circuit layouts and component configurations

Scripts

• Circuit Component Registry — Component registry for circuit mockups

---

<!-- PORTABILITY:START -->

Cross-Client Portability

This skill is written to stay usable across GitHub Copilot, Claude Code, Codex, and Gemini CLI.

• GitHub Copilot: keep the folder in a Copilot-visible skill or plugin path, or wrap the workflow as project instructions if the host does not support portable skill folders directly.
• Claude Code: keep the folder in a local skills directory or a compatible plugin or marketplace source.
• Codex: install or sync the folder into $CODEX_HOME/skills/<skill-name> and restart Codex after major changes.
• Gemini CLI: this repository generates a project command named /skills:legacy-circuit-mockups from this skill. Rebuild commands with python scripts/export-gemini-skill.py legacy-circuit-mockups and then run /commands reload inside Gemini CLI.

<!-- PORTABILITY:END -->

<!-- MCP:START -->

MCP Availability And Fallback

Preferred MCP Server: None required

• Fallback prompt: "Use the Legacy Circuit Mockups skill without MCP. Rely on the local SKILL.md, bundled references or scripts, and manual verification. Show the exact commands, evidence, and final checks you used before concluding."
• If the current host does not expose a matching server, use the bundled references, scripts, native toolchain, and manual workflow already described in this skill.
• Treat direct local verification, rendered output, logs, tests, or screenshots as the fallback evidence path before completion.

<!-- MCP:END -->

Related Skills

• frontend-design: Use it when the workflow also needs UI composition and front-end design direction.
• premium-frontend-ui: Use it when the workflow also needs high-fidelity UI polish and interaction detail.
• web-design-reviewer: Use it when the workflow also needs browser-based UI review and responsive QA.
• stitch-design: Use it when the workflow also needs turning interface designs into implementation-ready assets.

Changelog

[2026-04-25] - Version 1.2 Verification Protocol Refresh

Added

• Added a Verification Protocol section with skill-specific pass/fail checks, one pressure-test scenario, and a measurable success metric.
• Added guidance to leverage native parallel subagent dispatch and 200k+ context windows where available.

Changed

• Updated SKILL.md frontmatter to version: "1.2" and last_updated: 2026-04-25.
• Reframed activation guidance toward symptom -> action triggers and standardized two-stage review wording where applicable.

[2026-04-24] - Version 1.1 Refresh

Changed

• Updated the SKILL frontmatter version to 1.1 for the 2026-04-24 catalog refresh.

[2026-04-24] - Skill Refresh

Changed

• Standardized the SKILL frontmatter with version metadata, last-updated date, tags, and a concise catalog description.
• Reformatted the portability and MCP guidance with a preferred server line, a copy-paste fallback prompt, and consistent bullet lists.
• Added a catalog-standard Anti-Patterns section and refreshed the Related Skills links at the end of the skill.

[2026-04-24] - Catalog Audit Cleanup

Fixed

• Removed obsolete standalone Skill Paths guidance that duplicated the generated portability section.
• Normalized the Fairchild reference link to an external URL so repo-wide Markdown link validation does not treat it as a missing local file.

All notable changes to this skill will be documented in this file.

[2026-04-04] - Cross-Client Portability Refresh

Changed

• Added a standard portability note covering GitHub Copilot, Claude Code, Codex, and Gemini CLI.
• Clarified that the core workflow does not require a dedicated MCP server and can run with local tools alone.

Tested

• Validated SKILL.md frontmatter, portability sections, and Gemini export readiness with python scripts/validate-skills.py.

[2026-03-09] - Workspace Modernization

Added

• Added a 2026-03-09 maintenance entry after reviewing the skill; the existing structure and references remained suitable.

[2026-02-28] — Description Rewrite & Cross-References

Changed

• Rewrote skill description to ~200 characters with clear, specific activation keywords
• Improved keyword specificity to reduce overlap with related skills

Added

• ## Related Skills cross-reference table with 2-4 related skills and "Use When" guidance

Legacy Circuit Mockup Examples

Example 1: Single LED Circuit

Creating a basic LED circuit with current-limiting resistor:

// LED Circuit Component Layout
{
  components: [
    {
      type: 'led',
      x: 200,
      y: 200,
      color: 'red',
      properties: {
        forwardVoltage: 2.0,
        forwardCurrent: 20  // mA
      }
    },
    {
      type: 'resistor',
      x: 200,
      y: 240,
      ohms: 220,
      power: 0.25,  // Watts
      properties: {
        bands: 'red-red-brown-gold'  // 220Ω ±5%
      }
    }
  ],
  wires: [
    {
      start: { x: 100, y: 200 },  // +5V rail
      end: { x: 200, y: 200 },     // LED anode
      color: 'red'
    },
    {
      start: { x: 200, y: 240 },   // Resistor to LED cathode
      end: { x: 200, y: 260 },
      color: 'black'
    },
    {
      start: { x: 200, y: 260 },   // To GND
      end: { x: 100, y: 260 },
      color: 'black'
    }
  ]
}

// Resistor calculation: R = (Vcc - Vled) / Iled
// R = (5V - 2V) / 0.02A = 150Ω → use 220Ω (standard value)

Example 2: 555 Timer Astable Multivibrator

Creating a blinking LED circuit with 555 timer:

// 555 Astable Circuit
{
  components: [
    {
      type: 'ic-555',
      x: 300,
      y: 200,
      rotation: 0,
      properties: {
        pins: 8,
        mode: 'astable'
      }
    },
    {
      type: 'resistor',
      x: 360,
      y: 180,
      ohms: 10000,  // 10kΩ (R1)
      label: 'R1'
    },
    {
      type: 'resistor',
      x: 380,
      y: 220,
      ohms: 100000,  // 100kΩ (R2)
      label: 'R2'
    },
    {
      type: 'capacitor',
      x: 360,
      y: 260,
      farads: 10e-6,  // 10µF (C)
      type: 'electrolytic',
      label: 'C'
    },
    {
      type: 'led',
      x: 420,
      y: 200,
      color: 'green'
    }
  ],
  connections: [
    // Pin 1 (GND) → Ground rail
    { pin: 1, to: 'gnd' },
    // Pin 8 (Vcc) → +5V rail
    { pin: 8, to: 'vcc' },
    // Pin 4 (RESET) → Pin 8 (disable reset)
    { from: 4, to: 8 },
    // R1 between Pin 7 and Vcc
    { from: 'r1-start', to: 'vcc' },
    { from: 'r1-end', to: 7 },
    // R2 between Pin 7 and Pin 6
    { from: 'r2-start', to: 7 },
    { from: 'r2-end', to: 6 },
    // C between Pin 6 and GND
    { from: 6, to: 'c-positive' },
    { from: 'c-negative', to: 'gnd' },
    // Pin 2 (TRIG) connected to Pin 6 (THR)
    { from: 2, to: 6 },
    // Pin 3 (OUT) to LED
    { from: 3, to: 'led-anode' }
  ]
}

// Frequency calculation:
// f = 1.44 / ((R1 + 2×R2) × C)
// f = 1.44 / ((10000 + 200000) × 10e-6)
// f ≈ 0.69 Hz → ~1.5 second blink cycle

Example 3: 6502 Microprocessor Minimal System

Creating a minimal 6502 computer circuit:

// 6502 Minimal System Layout
{
  components: [
    // Microprocessor
    {
      type: 'ic-6502',
      x: 400,
      y: 300,
      properties: {
        pins: 40,
        label: 'W65C02S'
      }
    },
    // Program memory (EEPROM)
    {
      type: 'ic-28c256',
      x: 400,
      y: 100,
      properties: {
        pins: 28,
        capacity: '32KB',
        label: '28C256 EEPROM'
      }
    },
    // I/O Adapter
    {
      type: 'ic-6522',
      x: 600,
      y: 300,
      properties: {
        pins: 40,
        label: 'W65C22 VIA'
      }
    },
    // Clock crystal
    {
      type: 'crystal',
      x: 250,
      y: 320,
      frequency: 1000000,  // 1 MHz
      label: '1 MHz'
    },
    // Reset button
    {
      type: 'button',
      x: 200,
      y: 350,
      label: 'RESET'
    }
  ],
  buses: [
    // Address bus (A0-A15) - Blue wires
    {
      name: 'Address Bus',
      color: 'blue',
      lines: [
        { from: '6502-A0', to: 'EEPROM-A0' },
        { from: '6502-A1', to: 'EEPROM-A1' },
        // ... A2-A14
        { from: '6502-A15', to: 'CS-decoder' }
      ]
    },
    // Data bus (D0-D7) - Green wires
    {
      name: 'Data Bus',
      color: 'green',
      lines: [
        { from: '6502-D0', to: 'EEPROM-D0' },
        { from: '6502-D1', to: 'EEPROM-D1' },
        // ... D2-D6
        { from: '6502-D7', to: 'EEPROM-D7' }
      ]
    }
  ],
  control_signals: [
    // Clock - Yellow wire
    { name: 'PHI2', from: 'clock', to: '6502-PIN37', color: 'yellow' },
    // Read/Write - Orange wire
    { name: 'R/W', from: '6502-PIN34', to: 'EEPROM-W27', color: 'orange' },
    // Reset - White wire
    { name: 'RESB', from: 'reset-button', to: '6502-PIN40', color: 'white' }
  ]
}

Example 4: 7400 NAND Gate Logic

Creating a basic logic gate circuit:

// 7400 Quad 2-Input NAND Gate
{
  components: [
    {
      type: 'ic-7400',
      x: 300,
      y: 200,
      properties: {
        pins: 14,
        gates: 4,
        label: 'SN7400'
      }
    },
    {
      type: 'led',
      x: 400,
      y: 220,
      color: 'red',
      label: 'Output'
    },
    {
      type: 'switch',
      x: 200,
      y: 180,
      label: 'Input A'
    },
    {
      type: 'switch',
      x: 200,
      y: 240,
      label: 'Input B'
    }
  ],
  connections: [
    // Switch A to Gate 1 input A (Pin 1)
    { from: 'switch-a', to: 'pin-1' },
    // Switch B to Gate 1 input B (Pin 2)
    { from: 'switch-b', to: 'pin-2' },
    // Gate 1 output (Pin 3) to LED
    { from: 'pin-3', to: 'led-anode' },
    // Pin 7 to GND, Pin 14 to Vcc
    { pin: 7, to: 'gnd' },
    { pin: 14, to: 'vcc' }
  ]
}

// Truth table for NAND gate:
// A | B | Output
// 0 | 0 |   1
// 0 | 1 |   1
// 1 | 0 |   1
// 1 | 1 |   0

Example 5: Complete Breadboard Layout

Full breadboard with power rails and component placement:

// Complete Breadboard Layout
{
  breadboard: {
    width: 620,  // 31 columns × 20px
    height: 420, // 21 rows × 20px
    power_rails: {
      top: {
        positive: { y: 20, color: 'red' },
        negative: { y: 40, color: 'blue' }
      },
      bottom: {
        positive: { y: 380, color: 'red' },
        negative: { y: 400, color: 'blue' }
      }
    }
  },
  placement: [
    // IC placement (straddling center divide)
    {
      component: 'ic-555',
      position: { x: 200, y: 200 },
      orientation: 'horizontal',
      note: 'Pins 1-4 left, 5-8 right of center'
    },
    // Passive components
    {
      component: 'resistor-220',
      position: { x: 300, y: 180 },
      orientation: 'vertical'
    },
    {
      component: 'capacitor-10uF',
      position: { x: 320, y: 260 },
      orientation: 'vertical',
      note: 'Negative stripe to ground'
    },
    // Output
    {
      component: 'led-red',
      position: { x: 400, y: 220 },
      orientation: 'vertical',
      note: 'Long leg to positive, short leg to resistor'
    }
  ]
}

AT28C256 256K (32K x 8) Parallel EEPROM Specification

1. Overview

The AT28C256 is a non-volatile, electrically erasable and programmable read-only memory (EEPROM) manufactured by Atmel (now Microchip). It provides 256 Kbits of storage organized as 32,768 x 8 bits and is commonly used in 8-bit microprocessor systems such as those based on the 6502, Z80, and similar CPUs.

The device supports byte-level write operations, fast read access, and software-controlled data protection.

---

2. General Characteristics

---

3. Pin Configuration (Logical)

3.1 Address Pins (A0-A14)

• Select one of 32,768 memory locations

3.2 Data Pins (I/O0-I/O7)

• Bidirectional tri-state data bus
• Outputs valid during read cycles

3.3 Control Pins

---

4. Memory Organization

• Linear address space from $0000 to $7FFF
• Each address corresponds to one 8-bit byte

Address Range: 0000h - 7FFFh
Data Width:    8 bits

---

5. Read Operation

5.1 Read Cycle Conditions

• Data appears on I/O pins after access time
• Output remains valid while CE and OE are asserted
• Outputs are high-impedance when CE or OE is HIGH

---

6. Write Operation

6.1 Byte Write Cycle

• Address and data must be stable during WE low pulse
• Internal write cycle time ≈ 10 ms (max)
• Device automatically handles erase-before-write

---

7. Software Data Protection (SDP)

The AT28C256 includes optional Software Data Protection to prevent accidental writes.

7.1 SDP Enable Sequence

Write $AA to address $5555
Write $55 to address $2AAA
Write $A0 to address $5555

7.2 SDP Disable Sequence

Write $AA to address $5555
Write $55 to address $2AAA
Write $80 to address $5555
Write $AA to address $5555
Write $55 to address $2AAA
Write $20 to address $5555

---

8. Write Cycle Timing Notes

• Writes are internally timed; no external polling required
• During write cycle, reads return undefined data
• Device ignores additional write attempts while busy

---

9. Data Polling (Optional)

• I/O7 may be monitored during write
• When I/O7 matches written data, write is complete

---

10. Reset and Power Behavior

• No explicit reset pin
• Writes inhibited during power-up and power-down
• Outputs default to high-impedance until CE and OE asserted

---

11. Typical System Integration (6502 Example)

Address Range: $8000 - $FFFF
A15 used as chip select
OE  R/W?
WE  inverted R/W?

---

12. Absolute Maximum Ratings (Summary)

---

13. Variants and Compatible Devices

---

14. Common Use Cases

• ROM replacement in retro systems
• Firmware storage
• Microcomputer monitors and BASIC ROMs
• Prototyping and hobbyist computers

---

15. References

• <https://www.utmel.com/components/at28bv256-eeproms-pinout-equivalent-and-datasheet?id=1019>
• <https://www.futurlec.com/Memory/28C256.shtml>
• <https://ww1.microchip.com/downloads/en/DeviceDoc/doc0006.pdf>
• <https://bread80.com/2020/08/10/the-ben-eater-eeprom-programmer-28c256-and-software-data-protection/>

---

555

www.fairchildsemi.com

The LM555/NE555/SA555 is a highly stable controller capable of producing accurate timing pulses. With a monostable operation, the time delay is controlled by one external resistor and one capacitor. With an astable operation, the frequency and duty cycle are accurately controlled by two external resistors and one capacitor.

Features

• High Current Drive Capability (200mA)
• Adjustable Duty Cycle
• Temperature Stability of 0.005%/°C
• Timing From μSec to Hours
• Turn off Time Less Than 2μSec

Applications

• Precision Timing
• Pulse Generation
• Time Delay Generation
• Sequential Timing

Internal Block Diagram

flowchart TB
    subgraph IC["555 Timer IC"]
        direction TB
        
        subgraph DIVIDER["Voltage Divider"]
            R1["R (5kΩ)"]
            R2["R (5kΩ)"]
            R3["R (5kΩ)"]
            R1 --- R2 --- R3
        end
        
        COMP1["Comparator 1<br/>(Threshold)"]
        COMP2["Comparator 2<br/>(Trigger)"]
        FF["Flip-Flop<br/>S-R"]
        OUT_STAGE["Output<br/>Stage"]
        DISCH_TR["Discharge<br/>Transistor"]
        VREF["Vref"]
    end
    
    PIN8["Pin 8<br/>Vcc"] --> R1
    R3 --> PIN1["Pin 1<br/>GND"]
    
    R1 -.->|"2/3 Vcc"| COMP1
    R2 -.->|"1/3 Vcc"| COMP2
    
    PIN6["Pin 6<br/>Threshold"] --> COMP1
    PIN2["Pin 2<br/>Trigger"] --> COMP2
    
    COMP1 -->|R| FF
    COMP2 -->|S| FF
    
    FF --> OUT_STAGE
    FF --> DISCH_TR
    
    OUT_STAGE --> PIN3["Pin 3<br/>Output"]
    DISCH_TR --> PIN7["Pin 7<br/>Discharge"]
    
    PIN4["Pin 4<br/>Reset"] --> FF
    PIN5["Pin 5<br/>Control Voltage"] -.-> R2
    
    style PIN1 fill:#000,color:#fff
    style PIN2 fill:#f96,color:#000
    style PIN3 fill:#6f6,color:#000
    style PIN4 fill:#f66,color:#000
    style PIN5 fill:#ff6,color:#000
    style PIN6 fill:#6ff,color:#000
    style PIN7 fill:#f6f,color:#000
    style PIN8 fill:#f00,color:#fff

Pin Configuration:

Absolute Maximum Ratings (Ta = 25°C)

Electrical Characteristics

(TA = 250C, vcc = 5 15V, unless otherwise specified)

Notes:

1. When the output is high. the supply current is typically 1mA less than at VCC = 5V. 2. Tested at VCC = 5.0V and VCC = 15V. 3. This will determine the maximum value of RA + RB for 15V operation, the max- total R = 20MQ. and for 5V operation, the max/

• total R 8.7MΩ

4. These parameters, although guaranteed. are not 100% tested in production.

Application Information

Table 1 below is the basic operating table of 555 timer:

When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to threshold voltage and trigger voltage. When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr. turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.

1. Monostable Operation

Figure 1. Monostable Circuit

flowchart LR
    subgraph CIRCUIT["Monostable Configuration"]
        VCC["+Vcc"]
        
        subgraph TIMER["555 Timer"]
            P4["4<br/>RESET"]
            P8["8<br/>Vcc"]
            P7["7<br/>DISCH"]
            P2["2<br/>TRIG"]
            P6["6<br/>THRES"]
            P3["3<br/>OUT"]
            P5["5<br/>CONT"]
            P1["1<br/>GND"]
        end
        
        RA["RA"]
        C1["C1"]
        C2["C2<br/>0.01μF"]
        RL["RL"]
        GND["GND"]
    end
    
    VCC --> P4
    VCC --> P8
    VCC --> RA
    RA --> P7
    P7 --> P6
    P6 --> C1
    C1 --> GND
    
    TRIG_IN["Trigger<br/>Input"] --> P2
    
    P3 --> RL
    RL --> OUTPUT["Output"]
    
    P5 --> C2
    C2 --> GND
    P1 --> GND
    
    style VCC fill:#f00,color:#fff
    style GND fill:#000,color:#fff
    style TRIG_IN fill:#f96
    style OUTPUT fill:#6f6

Component Values:

• RA: Timing resistor (1kΩ to 10MΩ typical)
• C1: Timing capacitor
• C2: Bypass capacitor (0.01μF recommended)
• RL: Load resistor

Time Delay Formula: $$t_d = 1.1 \times R_A \times C_1$$

Figure 2. Resistance and Capacitance vs. Time Delay (td)

%%{init: {'theme': 'base', 'themeVariables': { 'primaryColor': '#fff', 'lineColor': '#333'}}}%%
xychart-beta
    title "Time Delay vs Capacitance (Log Scale)"
    x-axis "Time Delay (seconds)" [0.00001, 0.0001, 0.001, 0.01, 0.1, 1, 10, 100]
    y-axis "Capacitance (μF)" 0.001 --> 1000
    line "R=1kΩ" [0.001, 0.01, 0.1, 1, 10, 100, 1000, 10000]
    line "R=10kΩ" [0.0001, 0.001, 0.01, 0.1, 1, 10, 100, 1000]
    line "R=100kΩ" [0.00001, 0.0001, 0.001, 0.01, 0.1, 1, 10, 100]
    line "R=1MΩ" [0.000001, 0.00001, 0.0001, 0.001, 0.01, 0.1, 1, 10]

Figure 3. Waveforms of Monostable Operation

%%{init: {'theme': 'base'}}%%
gantt
    title Monostable Waveforms (Normal Operation)
    dateFormat X
    axisFormat %s
    
    section Trigger
    High (Vcc)    :a1, 0, 2
    Low (<Vcc/3)  :crit, a2, 2, 3
    High (Vcc)    :a3, 3, 10
    
    section Output
    Low (0V)      :b1, 0, 2
    High (Vcc)    :active, b2, 2, 8
    Low (0V)      :b3, 8, 10
    
    section Threshold (Vc1)
    Charging      :c1, 2, 8

    Trigger ─────┐     ┌─────────────────────
    (Pin 2)      └─────┘  
                    ↓ Trigger pulse
                    
    Output  ─────────┐          ┌───────────
    (Pin 3)         └──────────┘
                    |←── td ───→|
                    
    Threshold        /‾‾‾‾‾‾‾‾\
    (Pin 6)    ─────/          \────────────
               0V  ↗            ↘  
                  Vcc/3      2Vcc/3
                  
    td = 1.1 × RA × C1

Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1 and setting the flip-flop output at the same time. The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t=RAC and reaches 2Vcc/3 at td=1.1RAC. Hence, capacitor C1 is charged through resistor RA. The greater the time constant RAC, the longer it takes for the VC1 to reach 2Vcc/3. In other words, the time constant RAC controls the output pulse width. When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop, turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low. In this way, the timer operating in the monostable repeats the above process. Figure 2 shows the time constant relationship based on RA and C. Figure 3 shows the general waveforms during the monostable operation. It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse remains at below Vcc/3. Figure 4 shows such a timer output abnormality.

Figure 4. Waveforms of Monostable Operation (abnormal)

    Trigger ─────┐  ┌──┐  ┌─────────────────
    (Pin 2)      └──┘  └──┘  
                 ↓     ↓ Retriggering during output high
                    
    Output  ─────────┐                ┌─────
    (Pin 3)         └────────────────┘
                    |←── extended td ──→|
                    
    Threshold        /‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\
    (Pin 6)    ─────/                  \────
               0V  ↗                    ↘  
                  Vcc/3              2Vcc/3

    ⚠️ ABNORMAL: Trigger held low extends output pulse!
    Trigger must return high before output goes low.

Note: For normal operation, the trigger pulse voltage must return above Vcc/3 before the timer output goes low. If the trigger remains below Vcc/3, the output pulse will be extended abnormally.

2. Astable Operation

Figure 5. Astable Circuit

flowchart LR
    subgraph CIRCUIT["Astable Configuration"]
        VCC["+Vcc"]
        
        subgraph TIMER["555 Timer"]
            P4["4<br/>RESET"]
            P8["8<br/>Vcc"]
            P7["7<br/>DISCH"]
            P2["2<br/>TRIG"]
            P6["6<br/>THRES"]
            P3["3<br/>OUT"]
            P5["5<br/>CONT"]
            P1["1<br/>GND"]
        end
        
        RA["RA"]
        RB["RB"]
        C1["C1"]
        C2["C2<br/>0.01μF"]
        GND["GND"]
    end
    
    VCC --> P4
    VCC --> P8
    VCC --> RA
    RA --> P7
    P7 --> RB
    RB --> P6
    RB --> P2
    P6 --> C1
    C1 --> GND
    
    P3 --> OUTPUT["Output"]
    
    P5 --> C2
    C2 --> GND
    P1 --> GND
    
    MOD["Modulation<br/>(optional)"] -.-> P5
    
    style VCC fill:#f00,color:#fff
    style GND fill:#000,color:#fff
    style OUTPUT fill:#6f6
    style MOD fill:#ff6

Component Values:

• RA: Charge resistor (controls HIGH time)
• RB: Charge/discharge resistor (affects both HIGH and LOW times)
• C1: Timing capacitor
• C2: Bypass capacitor (0.01μF recommended)

Timing Formulas:

• High time: $t_H = 0.693 \times (R_A + R_B) \times C_1$
• Low time: $t_L = 0.693 \times R_B \times C_1$
• Period: $T = t_H + t_L = 0.693 \times (R_A + 2R_B) \times C_1$
• Frequency: $f = \frac{1.44}{(R_A + 2R_B) \times C_1}$
• Duty Cycle: $D = \frac{R_A + R_B}{R_A + 2R_B}$

Figure 6. Capacitance and Resistance vs. Frequency

%%{init: {'theme': 'base'}}%%
xychart-beta
    title "Free Running Frequency vs Capacitance"
    x-axis "Frequency (Hz)" [0.1, 1, 10, 100, 1000, 10000, 100000]
    y-axis "Capacitance (μF)" 0.001 --> 100

Figure 7. Waveforms of Astable Operation

    Output  ────┐     ┌─────┐     ┌─────┐     ┌────
    (Pin 3)    └─────┘     └─────┘     └─────┘
               |←tL→|←─tH─→|←tL→|←─tH─→|
               
    Threshold       /\        /\        /\
    (Pin 6)   ─────/  \──────/  \──────/  \──────
              Vcc/3    2Vcc/3
              
              ├────── T ──────┤
              T = tH + tL = 0.693(RA + 2RB)C1
              
    Charging:   C1 charges through RA + RB
    Discharging: C1 discharges through RB only

Typical Values: RA = 1kΩ, RB = 1kΩ, C1 = 1μF, Vcc = 5V

An astable timer operation is achieved by adding resistor RB to Figure 1 and configuring as shown on Figure 5. In the astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi vibrator. When the timer output is high, its internal discharging Tr. turns off and the VC1 increases by exponential function with the time constant (RA+RB)*C. When the VC1, or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high, resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 discharges through the discharging channel formed by RB and the discharging Tr. When the VC1 falls below Vcc/3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the VC1 rises again. In the above process, the section where the timer output is high is the time it takes for the VC1 to rise from Vcc/3 to 2Vcc/3, and the section where the timer output is low is the time it takes for the VC1 to drop from 2Vcc/3 to Vcc/3. When timer output is high, the equivalent circuit for charging capacitor C1 is as follows:

Equation 1: Charging Circuit Equivalent

flowchart LR
    VCC["Vcc"] --> RA_RB["RA + RB"]
    RA_RB --> C1["C1<br/>Vc1(0-)=Vcc/3"]
    C1 --> GND["GND"]

Charging Equation: $$C_1 \frac{dV_{C1}}{dt} = \frac{V_{CC} - V_{(0-)}}{R_A + R_B} \quad (1)$$

$$V_{C1}(0^+) = \frac{V_{CC}}{3} \quad (2)$$

$$V_{C1}(t) = V_{CC} \left[ 1 - \frac{2}{3} e^{-\frac{t}{(R_A + R_B)C_1}} \right] \quad (3)$$

Since the duration of the timer output high state (tH) is the amount of time it takes for the VC1(t) to reach 2Vcc/3,

Equation 2: High Time Calculation

$$\frac{2}{3}V_{CC} = V_{CC} \left[ 1 - \frac{2}{3} e^{-\frac{t_H}{(R_A + R_B)C_1}} \right] \quad (4)$$

$$t_H = C_1(R_A + R_B) \ln 2 = 0.693(R_A + R_B)C_1 \quad (5)$$

The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows:

Equation 3: Discharging Circuit Equivalent

flowchart LR
    C1["C1<br/>Vc1(0-)=2Vcc/3"] --> RB["RB"]
    RB --> RD["RD<br/>(discharge Tr.)"]
    RD --> GND["GND"]

Discharging Equation: $$C_1 \frac{dV_{C1}}{dt} + \frac{1}{R_A + R_B} V_{C1} = 0 \quad (6)$$

$$V_{C1}(t) = \frac{2}{3} V_{CC} e^{-\frac{t}{(R_A + R_B)C_1}} \quad (7)$$

Since the duration of the timer output low state (tL) is the amount of time it takes for the VC1(t) to reach Vcc/3,

Equation 4: Low Time Calculation

$$\frac{1}{3}V_{CC} = \frac{2}{3}V_{CC} e^{-\frac{t_L}{(R_B + R_D)C_1}} \quad (8)$$

$$t_L = C_1(R_B + R_D) \ln 2 = 0.693(R_A + R_B)C_1 \quad (9)$$

Since RD is normally RB>>RD although related to the size of discharging Tr., tL=0.693RBC1 (10) Consequently, if the timer operates in astable, the period is the same with 'T=tH+tL=0.693(RA+RB)C1+0.693RBC1=0.693(RA+2RB)C1' because the period is the sum of the charge time and discharge time. And since frequency is the reciprocal of the period, the following applies.

Equation 5: Frequency Formula

$$f = \frac{1}{T} = \frac{1.44}{(R_A + 2R_B)C_1} \quad (11)$$

3. Frequency divider

By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure 8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.

Figure 8. Waveforms of Frequency Divider Operation

    Trigger ─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
    (Input)  └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘
             1   2   3   1   2   3   1   2   3
             
    Output  ─┐        ┌──┐        ┌──┐        ┌──────
    (÷3)     └────────┘  └────────┘  └────────┘
             |← skip →|  |← skip →|  |← skip →|
                2,3          2,3         2,3
                
    Threshold      /‾‾‾‾\        /‾‾‾‾\        /‾‾‾‾\
    (Vc1)    ─────/      \──────/      \──────/
             
    RA = 9.1kΩ, RB = 1kΩ, C1 = 0.01μF, Vcc = 5V
    
    ⚙️ Divide-by-N: Set timing so output ignores (N-1) trigger pulses

4. Pulse Width Modulation

The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the reference of the timer's internal comparators. Figure 9 illustrates the pulse width modulation circuit. When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated according to the signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the control terminal. Figure 10 shows the example of pulse width modulation waveform.

Figure 9. Circuit for Pulse Width Modulation

flowchart LR
    subgraph CIRCUIT["PWM Configuration"]
        VCC["+Vcc"]
        
        subgraph TIMER["555 Timer"]
            P4["4<br/>RESET"]
            P8["8<br/>Vcc"]
            P7["7<br/>DISCH"]
            P2["2<br/>TRIG"]
            P6["6<br/>THRES"]
            P3["3<br/>OUT"]
            P5["5<br/>CONT"]
            P1["1<br/>GND"]
        end
        
        RA["RA"]
        C1["C1"]
        C2["C2"]
        GND["GND"]
    end
    
    VCC --> P4
    VCC --> P8
    VCC --> RA
    RA --> P7
    P7 --> P6
    P6 --> C1
    C1 --> GND
    
    TRIG_IN["Trigger<br/>Pulse Train"] --> P2
    MOD["Modulation<br/>Signal"] --> P5
    P5 --> C2
    C2 --> GND
    
    P3 --> OUTPUT["PWM<br/>Output"]
    P1 --> GND
    
    style VCC fill:#f00,color:#fff
    style GND fill:#000,color:#fff
    style TRIG_IN fill:#f96
    style MOD fill:#ff6
    style OUTPUT fill:#6f6

Figure 10. Waveforms of Pulse Width Modulation

    Control  ╭──────╮      ╭──────╮      ╭──────╮
    (Pin 5)  │      │      │      │      │      │
          ───╯      ╰──────╯      ╰──────╯      ╰───
             |← Modulation Signal (e.g., Sine) →|
                    
    Trigger ─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
             └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘
             
    Output  ─┐  ┌─┐   ┌───┐   ┌─┐  ┌─┐   ┌───┐   ┌─
    (PWM)    └──┘ └───┘   └───┘ └──┘ └───┘   └───┘
             |←w1→|←w2─→|←w3──→|
             
    Pulse width varies with control voltage:
    - Higher control voltage → Longer pulse width
    - Lower control voltage → Shorter pulse width
    
    RA = 3.9kΩ, RB = 1kΩ, RL = 1kΩ, C1 = 0.01μF, Vcc = 5V

5. Pulse Position Modulation

If the modulating signal is applied to the control terminal while the timer is connected for the astable operation as in Figure 11, the timer becomes a pulse position modulator. In the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the timer output according to the modulation signal applied to the control terminal. Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave shape could be used.

Figure 11. Circuit for Pulse Position Modulation

flowchart LR
    subgraph CIRCUIT["PPM Configuration"]
        VCC["+Vcc"]
        
        subgraph TIMER["555 Timer"]
            P4["4<br/>RESET"]
            P8["8<br/>Vcc"]
            P7["7<br/>DISCH"]
            P2["2<br/>TRIG"]
            P6["6<br/>THRES"]
            P3["3<br/>OUT"]
            P5["5<br/>CONT"]
            P1["1<br/>GND"]
        end
        
        RA["RA"]
        RB["RB"]
        C1["C1"]
        GND["GND"]
    end
    
    VCC --> P4
    VCC --> P8
    VCC --> RA
    RA --> P7
    P7 --> RB
    RB --> P6
    RB --> P2
    P6 --> C1
    C1 --> GND
    
    MOD["Modulation<br/>Signal"] --> P5
    
    P3 --> OUTPUT["PPM<br/>Output"]
    P1 --> GND
    
    style VCC fill:#f00,color:#fff
    style GND fill:#000,color:#fff
    style MOD fill:#ff6
    style OUTPUT fill:#6f6

Figure 12. Waveforms of Pulse Position Modulation

    Control  ╭────────────╮          ╭────────────╮
    (Pin 5)  │            │          │            │
          ───╯            ╰──────────╯            ╰───
                Modulation Signal (Sine Wave)
                    
    Threshold     /\    /\      /\      /\    /\
    (Pin 6)  ────/  \──/  \────/  \────/  \──/  \────
                        
    Output  ─┐ ┌─┐  ┌──┐    ┌────┐    ┌──┐  ┌─┐ ┌─
    (PPM)    └─┘ └──┘  └────┘    └────┘  └──┘ └─┘
             |←t1→|←t2─→|←─t3──→|←t4─→|←t5→|
             
    Pulse spacing varies with control voltage:
    - Higher control voltage → Longer period
    - Lower control voltage → Shorter period
    
    RA = 1kΩ, RB = 1kΩ, C1 = 1nF, Vcc = 5V

6. Linear Ramp

When the pull-up resistor RA in the monostable circuit shown in Figure 1 is replaced with constant current source, the VC1 increases linearly, generating a linear ramp. Figure 13 shows the linear ramp generating circuit and Figure 14 illustrates the generated linear ramp waveforms.

Figure 13. Circuit for Linear Ramp

flowchart TB
    subgraph CIRCUIT["Linear Ramp Generator"]
        VCC["+Vcc"]
        
        subgraph CURRENT_SOURCE["Constant Current Source"]
            RE["RE"]
            Q1["Q1<br/>PNP"]
            R1["R1"]
            R2["R2"]
        end
        
        subgraph TIMER["555 Timer"]
            P4["4<br/>RESET"]
            P8["8<br/>Vcc"]
            P7["7<br/>DISCH"]
            P2["2<br/>TRIG"]
            P6["6<br/>THRES"]
            P3["3<br/>OUT"]
            P5["5<br/>CONT"]
            P1["1<br/>GND"]
        end
        
        C1["C1"]
        C2["C2"]
        GND["GND"]
    end
    
    VCC --> P4
    VCC --> P8
    VCC --> RE
    VCC --> R1
    
    RE --> Q1
    R1 --> Q1
    Q1 --> R2
    R2 --> GND
    
    Q1 -->|Ic| P7
    P7 --> P6
    P6 --> C1
    C1 --> GND
    
    TRIG_IN["Trigger"] --> P2
    
    P3 --> OUTPUT["Output"]
    P5 --> C2
    C2 --> GND
    P1 --> GND
    
    style VCC fill:#f00,color:#fff
    style GND fill:#000,color:#fff
    style Q1 fill:#fcf,color:#000
    style OUTPUT fill:#6f6

Figure 14. Waveforms of Linear Ramp

    Trigger ─────┐     ┌───────────────────────────
    (Pin 2)      └─────┘  
                    ↓ Trigger pulse
                    
    Output  ─────────┐              ┌───────────────
    (Pin 3)         └──────────────┘
                    |←──── td ────→|
                    
    Threshold        ╱              Linear ramp (not exponential)
    (Pin 6)    ─────╱               
               0V  ↗                 
                  Vcc/3           2Vcc/3
                  
    Linear ramp: Vc1 = (Ic/C1) × t
    Slope S = Ic/C1
    
    R1 = 47kΩ, R2 = 100kΩ, RE = 2.7kΩ, RL = 1kΩ, C1 = 0.01μF, Vcc = 5V

In Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and RE.

Equation 6: Current Source Calculation

$$I_C = \frac{V_{CC} - V_E}{R_E} \quad (12)$$

Here, VE is:

$$V_E = V_{BE} + \frac{R_2}{R_1 + R_2} V_{CC} \quad (13)$$

For example, if Vcc=15V, RE=20kΩ, R1=5kW, R2=10kΩ, and VBE=0.7V, VE=0.7V+10V=10.7V Ic=(15-10.7)/20k=0.215mA

When the trigger starts in a timer configured as shown in Figure 13, the current flowing through capacitor C1 becomes a constant current generated by PNP transistor and resistors. Hence, the VC is a linear ramp function as shown in Figure 14. The gradient S of the linear ramp function is defined as follows:

Equation 7: Ramp Slope

$$S = \frac{V_{P-P}}{T} \quad (14)$$

Here the Vp-p is the peak-to-peak voltage. If the electric charge amount accumulated in the capacitor is divided by the capacitance, the VC comes out as follows:

V = Q/C (15)

The above equation divided on both sides by T gives us

Equation 8: Simplified Ramp Slope

$$\frac{V}{T} = \frac{Q/T}{C} \quad (16)$$

and may be simplified into the following equation.

S = I/C (17)

In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant current flowing through the capacitor. If the constant current flow through the capacitor is 0.215mA and the capacitance is 0.02μF, the gradient of the ramp function at both ends of the capacitor is S = 0.215m/0.022μ = 9.77V/ms.

Mechanical Dimensions

Package

8-DIP (Dual In-line Package)

    ┌─────────────────────────────────────┐
    │  ●                                  │
    │  #1                             #8  │
    │  ┌──┐                         ┌──┐  │
    │  │  │                         │  │  │
    │  └──┘                         └──┘  │
    │  #2                             #7  │
    │  ┌──┐       555 TIMER         ┌──┐  │
    │  │  │                         │  │  │
    │  └──┘                         └──┘  │
    │  #3                             #6  │
    │  ┌──┐                         ┌──┐  │
    │  │  │                         │  │  │
    │  └──┘                         └──┘  │
    │  #4                             #5  │
    │  ┌──┐                         ┌──┐  │
    │  │  │                         │  │  │
    │  └──┘                         └──┘  │
    └─────────────────────────────────────┘

8-DIP Dimensions (in millimeters):

              6.40 ± 0.20
         ┌────────────────┐
         │                │
    ┌────┤                ├────┐
    │    │                │    │  9.60
    │    │                │    │  MAX
    │    │                │    │
    └────┤                ├────┘
         │                │
         └────────────────┘
              ↕ 2.54 (pin pitch)
         
    Side View:
         ┌────────────────┐
    5.08 │                │
    MAX  └──┬──┬──┬──┬──┬─┘
            │  │  │  │  │   3.30 ± 0.30
            │  │  │  │  │   (lead length)
         ═══╧══╧══╧══╧══╧═══
                ↕ 0.33 MIN

8-SOP (Small Outline Package)

    ┌───────────────────────────────┐
    │  ●                            │
    │  #1                       #8  │
    │  ─┐                       ┌─  │
    │   │                       │   │
    ├───┴───────────────────────┴───┤
    │           555 TIMER           │
    ├───┬───────────────────────┬───┤
    │   │                       │   │
    │  ─┘                       └─  │
    │  #4                       #5  │
    └───────────────────────────────┘

8-SOP Dimensions (in millimeters):

              6.00 ± 0.30
         ┌────────────────┐
    ─┐   │                │   ┌─
     │   │                │   │   4.92 ± 0.20
    ─┘   │                │   └─
         └────────────────┘
              ↕ 1.27 (pin pitch)
         
    Side View:
              1.55 ± 0.20
         ┌────────────────┐
    MAX  │                │
         └──┬──┬──┬──┬──┬─┘
            └──┴──┴──┴──┴── 0.10~0.25 standoff

Pin Assignment Summary

MOS Technology 6502 Microprocessor Specification

1. Overview

The MOS Technology 6502 is an 8-bit microprocessor introduced in 1975. It is notable for its low cost, efficient instruction set, and widespread use in early personal computers and game consoles, including the Apple II, Commodore 64, Atari 2600, NES (Ricoh 2A03 variant), and BBC Micro.

---

2. General Characteristics

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3. Programmer-Visible Registers

3.1 Accumulator (A)

• 8-bit register
• Used for arithmetic, logic, and data transfer operations

3.2 Index Registers (X, Y)

• 8-bit registers
• Used for indexing memory, counters, and offsets

3.3 Stack Pointer (SP)

• 8-bit register
• Points to the current stack location
• Stack resides in page $0100–$01FF

3.4 Program Counter (PC)

• 16-bit register
• Holds address of next instruction

3.5 Processor Status Register (P)

---

4. Memory Map Conventions

4.1 Interrupt Vectors

---

5. Addressing Modes

---

6. Instruction Set Summary

6.1 Load / Store

• LDA, LDX, LDY
• STA, STX, STY

6.2 Register Transfers

• TAX, TAY, TXA, TYA, TSX, TXS

6.3 Stack Operations

• PHA, PLA, PHP, PLP

6.4 Arithmetic

• ADC – Add with Carry
• SBC – Subtract with Carry

6.5 Logical

• AND, ORA, EOR

6.6 Shifts and Rotates

• ASL, LSR, ROL, ROR

6.7 Increment / Decrement

• INC, INX, INY
• DEC, DEX, DEY

6.8 Comparisons

• CMP, CPX, CPY

6.9 Branching

• BEQ, BNE, BMI, BPL, BCS, BCC, BVS, BVC

6.10 Jumps & Subroutines

• JMP, JSR, RTS, RTI

6.11 Status Flag Control

• CLC, SEC, CLI, SEI, CLV, CLD, SED

6.12 System Control

• BRK, NOP

---

7. Cycle Timing (General)

• Most instructions execute in 2–7 cycles
• Additional cycles may be added for:

• Page boundary crossings
• Taken branches

---

8. Decimal Mode

When the D flag is set:

• ADC and SBC operate using BCD arithmetic
• Only valid on NMOS 6502 (behavior varies on CMOS derivatives)

---

9. Known Hardware Quirks

• JMP (addr) indirect bug: page boundary wraparound

• Example: JMP ($10FF) reads from $10FF and $1000
• No dedicated multiply or divide instructions
• Stack is fixed to page $01xx

---

10. Variants and Derivatives

---

11. Example Code

        LDX #$00
loop:   INX
        TXA
        STA $0200,X
        CPX #$10
        BNE loop
        BRK

---

12. References

• <https://syncopate.us/books/Synertek6502ProgrammingManual.html>
• <https://en.wikipedia.org/wiki/MOS_Technology_6502>
• <https://web.archive.org/web/20061114024257/http://www.westerndesigncenter.com/wdc/documentation/Programmanual.pdf>
• Tutorial excerpts from <https://wilsonminesco.com/6502primer/>
• <https://wilsonminesco.com/6502primer/LogicFamilies.html>
• <https://wilsonminesco.com/6502primer/ClkGen.html>
• <https://wilsonminesco.com/6502primer/RSTreqs.html>
• <https://wilsonminesco.com/6502primer/displays.html>
• <https://wilsonminesco.com/6502primer/debug.html>
• <https://wilsonminesco.com/6502primer/potpourri.html>

---

MOS Technology 6522 Versatile Interface Adapter (VIA)

1. Overview

The MOS Technology 6522 VIA is a general-purpose I/O controller designed to interface the 6502 family of microprocessors with external peripherals. Introduced in the mid-1970s, it provides parallel I/O ports, timers, shift register support, and interrupt handling. The 6522 is widely used in systems such as the Commodore PET, VIC-20, Apple II, BBC Micro, and many 6502-based embedded designs.

---

2. General Characteristics

---

3. Pin Functions (Logical)

3.1 Port A (PA0-PA7)

• 8-bit bidirectional parallel I/O
• Handshake support via CA1 / CA2

3.2 Port B (PB0-PB7)

• 8-bit bidirectional parallel I/O
• Handshake support via CB1 / CB2
• PB6 and PB7 may be controlled by Timer 1

3.3 Control Pins

---

4. Register Map

Registers are selected using 4 address lines (RS0-RS3). The base address is system-defined.

---

5. Data Direction Registers (DDRA / DDRB)

Each bit controls the direction of its corresponding port pin:

• 0 = Input
• 1 = Output

DDRB bit = 1  PBx is output
DDRB bit = 0  PBx is input

---

6. Timers

6.1 Timer 1 (T1)

• 16-bit down counter
• Can operate in one-shot or free-running mode
• Can toggle PB7 on timeout
• Generates interrupts

6.2 Timer 2 (T2)

• 16-bit down counter
• Supports pulse counting on PB6
• One-shot operation only

---

7. Shift Register (SR)

• 8-bit shift register
• Can shift data in or out
• Clock source selectable via ACR
• Often used for serial communication or keyboard scanning

---

8. Control Registers

8.1 Auxiliary Control Register (ACR)

8.2 Peripheral Control Register (PCR)

Controls CA1, CA2, CB1, CB2 behavior:

• Input/output mode
• Active edge selection
• Pulse or handshake modes

---

9. Interrupt System

9.1 Interrupt Flag Register (IFR)

9.2 Interrupt Enable Register (IER)

• Bit 7 determines set/clear mode:

• 1 = set bits
• 0 = clear bits

Write $80 | mask  enable interrupts
Write $00 | mask  disable interrupts

---

10. Reset Behavior

On RESET:

• All DDR bits cleared (ports default to input)
• Timers stopped
• Shift register disabled
• Interrupts disabled

---

11. Timing Notes

• VIA registers are accessed synchronously with φ2
• Timer counters decrement once per φ2 cycle
• Some operations have side effects when reading/writing registers

---

12. Common Use Cases

• Keyboard and joystick interfaces
• Parallel printer interfaces
• Timers and event counting
• Simple serial communications
• General-purpose GPIO expansion

---

13. Variants and Related Chips

---

14. References

• <https://en.wikipedia.org/wiki/MOS_Technology_6522>
• <https://grokipedia.com/page/MOS_Technology_6522>

---

AS6C62256 32K x 8 Low-Power CMOS SRAM Specification

1. Overview

The AS6C62256 is a 256 Kbit (32K x 8) low-power CMOS static random-access memory (SRAM) manufactured by Alliance Memory (and second-sourced by others). It is fully compatible with common 28-pin SRAM pinouts and is widely used in 6502, Z80, and other 8-bit microprocessor systems for read/write memory.

The device offers fast access times, simple control logic, and very low standby power consumption.

---

2. General Characteristics

---

3. Pin Configuration (Logical)

3.1 Address Pins (A0-A14)

• Select one of 32,768 memory locations
• Address must be stable during read or write cycle

3.2 Data Pins (I/O0-I/O7)

• Bidirectional tri-state data bus
• High-impedance when not enabled

3.3 Control Pins

---

4. Memory Organization

• Linear address space from $0000 to $7FFF
• Each address corresponds to one byte (8 bits)

Address range: 0000h - 7FFFh
Data width:    8 bits

---

5. Read Operation

5.1 Read Cycle Conditions

• Data becomes valid after access time (tAA)
• Outputs remain valid while CE? and OE? are LOW
• Outputs are high-impedance when CE? or OE? is HIGH

---

6. Write Operation

6.1 Write Cycle Conditions

• Data is written on the rising edge of WE? or CE?
• Address and data must be stable during write window
• No internal write delay (true SRAM behavior)

---

7. Timing Notes (Summary)

---

8. Power Modes

8.1 Active Mode

• CE? = LOW
• Normal read/write operation

8.2 Standby Mode

• CE? = HIGH
• Data retained
• Very low power consumption

---

9. Reset and Power-Up Behavior

• No reset pin required
• Data is undefined at power-up
• Memory contents preserved only while VCC is present

---

10. Typical System Integration (6502 Example)

Mapped at:     $0000 - $7FFF
CE?   decoded address
OE?   R/W?
WE?   inverted R/W?

---

11. Absolute Maximum Ratings (Summary)

---

12. Compatible and Equivalent Devices

---

13. Common Use Cases

• Main RAM for 6502 / Z80 systems
• Video buffers and frame memory
• Embedded systems requiring fast R/W memory
• Retrocomputer SBC designs

---

14. References

• <https://www.alliancememory.com/wp-content/uploads/AS6C62256-23-March-2016-rev1.2.pdf>
• <https://www.futurlec.com/Datasheet/Memory/62256.pdf>
• <https://www.malinov.com/sergeys-blog/homebrew-notes.html>

---

7400-Series Logic ICs Specification

1. Overview

The 7400-series is a large family of digital logic integrated circuits originally implemented in TTL (Transistor-Transistor Logic) and later expanded to include CMOS-compatible variants. These devices provide fundamental building blocks such as gates, flip-flops, counters, multiplexers, decoders, and bus transceivers.

7400-series ICs are widely used in retrocomputing, 6502/Z80 systems, glue logic, and educational designs.

---

2. Logic Families

---

3. Electrical Characteristics (Typical)

---

4. Standard Package Types

---

5. Common Logic Categories

5.1 Basic Logic Gates

---

5.2 Latches and Flip-Flops

---

5.3 Counters and Registers

---

5.4 Decoders and Multiplexers

---

5.5 Bus Interface and Glue Logic

---

6. Pin Numbering Convention

• DIP packages use counter-clockwise numbering
• Pin 1 identified by notch or dot

       ________
  1 °|       |° 14
  2 °|        |° 13
  3 °|        |° 12
  4 °|        |° 11
  5 °|        |° 10
  6 °|        |°  9
  7 °|________|°  8

---

7. Power and Ground Pins

---

8. Timing Characteristics (General)

---

9. Interfacing Notes

• TTL outputs reliably drive TTL inputs
• CMOS inputs must not float
• Use 74HCT when interfacing CMOS with TTL signals
• Decoupling capacitors (0.1 µF) required per IC

---

10. Typical Retrocomputer Applications

• Address decoding
• Chip-select generation
• Bus buffering
• Clock gating and control
• State machines

---

11. Absolute Maximum Ratings (Summary)

---

12. References

• <https://www.ti.com/lit/ds/symlink/sn74ls00.pdf>
• <https://archive.org/details/TTLCookBook>
• <https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide>

---

6502 SBC Assembly Compilation & ROM Build Specification

Overview

This document defines a complete specification for compiling 6502 assembly language for a single-board computer consisting of:

• MOS 6502 CPU
• MOS 6522 VIA
• AS6C62256 (32 KB SRAM)
• AT28C256 (32 KB EEPROM / ROM)
• DFRobot FIT0127 (HD44780-compatible 16x2 LCD)

The focus is on toolchain behavior, memory layout, ROM construction, and firmware conventions, not electrical wiring.

---

Target System Architecture

Memory Map (Canonical)

$0000-$00FF  Zero Page (RAM)
$0100-$01FF  Stack (RAM)
$0200-$7FFF  General RAM (AS6C62256)
$8000-$8FFF  6522 VIA I/O space
$9000-$FFFF  ROM (AT28C256)

Address decoding may mirror devices; assembler assumes this canonical layout.

---

ROM Organization (AT28C256)

ROM image size: 32,768 bytes

---

Reset & Startup Convention

On reset:

1. CPU fetches RESET vector at $FFFC 2. Code initializes stack pointer 3. Zero-page variables initialized 4. VIA configured 5. LCD initialized 6. Main program entered

---

Assembler Requirements

Assembler MUST support:

• .org absolute addressing
• Symbolic labels
• Binary output (.bin)
• Little-endian word emission
• Zero-page optimization

Recommended assemblers:

• ca65 (cc65 toolchain)
• vasm6502
• 64tass

---

Assembly Source Structure

;---------------------------
; Reset Vector Entry Point
;---------------------------
        .org $9000
RESET:
        sei
        cld
        ldx #$FF
        txs
        jsr init_via
        jsr init_lcd
MAIN:
        jsr lcd_print
        jmp MAIN

---

Vector Table Definition

        .org $FFFA
        .word nmi_handler
        .word RESET
        .word irq_handler

---

6522 VIA Programming Model

Register Map (Base = $8000)

---

LCD Interface Convention

LCD Wiring Assumption

4-bit mode assumed.

---

LCD Initialization Sequence

lcd_init:
        lda #$33
        jsr lcd_cmd
        lda #$32
        jsr lcd_cmd
        lda #$28
        jsr lcd_cmd
        lda #$0C
        jsr lcd_cmd
        lda #$06
        jsr lcd_cmd
        lda #$01
        jsr lcd_cmd
        rts

---

LCD Command/Data Interface

---

Zero Page Usage Convention

---

RAM Usage (AS6C62256)

• Stack uses page $01
• All RAM assumed volatile
• No ROM shadowing

---

Build Pipeline

Step 1: Assemble

ca65 main.asm -o main.o

Step 2: Link

ld65 -C rom.cfg main.o -o rom.bin

Step 3: Pad ROM

Ensure rom.bin is exactly 32768 bytes.

---

EEPROM Programming

• Target device: AT28C256
• Programmer: MiniPro / T48
• Verify after write

---

Emulator Expectations

Emulator must:

• Load ROM at $9000-$FFFF
• Emulate VIA I/O side effects
• Render LCD output
• Honor RESET vector

---

Testing Checklist

• Reset vector execution
• VIA register writes
• LCD displays correct text
• Stack operations valid
• ROM image maps correctly

---

References

• MOS 6502 Programming Manual
• MOS 6522 VIA Datasheet
• AT28C256 Datasheet
• HD44780 LCD Datasheet
• cc65 Toolchain Docs

---

Notes

This specification is intentionally end-to-end: from assembly source to EEPROM image to running hardware or emulator. It defines a stable contract so ROMs, emulators, and real SBCs behave identically.

6502 Assembly Language with AT28C256 EEPROM

A practical specification for writing 6502/65C02 assembly language programs intended to be stored in and executed from an AT28C256 (32 KB) parallel EEPROM in single-board computers (SBCs) and retro systems.

---

1. Scope and Assumptions

This document assumes:

• A 6502-family CPU (6502, 65C02, or compatible)
• Program code stored in an AT28C256 (32K x 8) EEPROM
• Memory-mapped I/O (e.g., 6522 VIA)
• Reset and interrupt vectors located in EEPROM
• External RAM mapped elsewhere (e.g., 62256 SRAM)

---

2. AT28C256 EEPROM Overview

Typical Memory Map Usage

---

3. 6502 Memory Map Example

$0000-$00FF  Zero Page (RAM)
$0100-$01FF  Stack
$0200-$7FFF  RAM / I/O
$8000-$FFFF  AT28C256 EEPROM

---

4. Reset and Interrupt Vectors

The 6502 reads vectors from the top of memory:

Vector Definition Example

        .org $FFFA
        .word nmi_handler
        .word reset
        .word irq_handler

---

5. Assembly Program Structure

Typical Layout

        .org $8000

reset:
        sei             ; Disable IRQs
        cld             ; Clear decimal mode
        ldx #$FF
        txs             ; Initialize stack

main:
        jmp main

---

6. Essential 6502 Instructions

Registers

Common Instructions

---

7. Addressing Modes (Common)

---

8. Writing Code for EEPROM Execution

Key Considerations

• Code is read-only at runtime
• Self-modifying code not recommended
• Place jump tables and constants in EEPROM
• Use RAM for variables and stack

Zero Page Variable Example

counter = $00

        lda #$00
        sta counter

---

9. Timing and Performance

• EEPROM access time must meet CPU clock requirements
• AT28C256 supports ~1 MHz comfortably
• Faster clocks may require wait states or ROM shadowing

---

10. Example: Simple LED Toggle (Memory-Mapped I/O)

PORTB = $6000
DDRB  = $6002

        .org $8000
reset:
        sei
        ldx #$FF
        txs

        lda #$FF
        sta DDRB

loop:
        lda #$FF
        sta PORTB
        jsr delay
        lda #$00
        sta PORTB
        jsr delay
        jmp loop

---

11. Assembling and Programming Workflow

1. Write source (.asm) 2. Assemble to binary 3. Pad or relocate to $8000 4. Program AT28C256 via T48 / minipro 5. Insert EEPROM and reset CPU

---

12. Assembler Directives (Common)

---

13. Common Mistakes

---

14. Reference Links

• https://www.masswerk.at/6502/6502_instruction_set.html
• https://www.nesdev.org/wiki/6502
• https://www.westerndesigncenter.com/wdc/documentation
• https://en.wikipedia.org/wiki/MOS_Technology_6502

---

Document Scope: 6502 assembly stored in AT28C256 EEPROM Audience: Retrocomputing, SBC designers, embedded hobbyists Status: Stable reference

Basic Electronic Components

This document covers four fundamental electronic components: Resistors, Capacitors, Buttons, and Switches, including common values, formulas, and types.

---

1. Resistors (R)

Resistors limit the flow of electrical current and dissipate energy as heat.

Common Formulas

• Ohm's Law: $V = I \times R$ (Voltage = Current $\times$ Resistance)
• Series Resistance: $R_{total} = R_1 + R_2 + ... + R_n$
• Parallel Resistance: $\frac{1}{R_{total}} = \frac{1}{R_1} + \frac{1}{R_2} + ... + \frac{1}{R_n}$

Common Values (E12/E24 Series - 5% Tolerance)

Values are multiplied by powers of 10 (e.g., 10$\Omega$, 100$\Omega$, 1k$\Omega$, 10k$\Omega$, 100k$\Omega$, 1M$\Omega$): 1.0, 1.1, 1.2, 1.3, 1.5, 1.6, 1.8, 2.0, 2.2, 2.4, 2.7, 3.0, 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1

---

2. Capacitors (C)

Capacitors store electrical charge in an electric field.

Common Formulas

• Capacitance: $C = \frac{Q}{V}$ (Charge / Voltage)
• Current: $i = C \frac{dV}{dt}$
• Parallel Capacitance: $C_{total} = C_1 + C_2 + ... + C_n$
• Series Capacitance: $\frac{1}{C_{total}} = \frac{1}{C_1} + \frac{1}{C_2} + ... + \frac{1}{C_n}$
• Energy Stored: $W = \frac{1}{2} C V^2$

Common Values

• Ceramic (picoFarads/nanoFarads): 10pF, 22pF, 100pF, 1nF, 10nF, 100nF (often labeled "104")
• Electrolytic (microFarads): 1µF, 10µF, 22µF, 47µF, 100µF, 220µF, 470µF, 1000µF

---

3. Buttons (Push Button)

A momentary switch that completes a circuit only when pressed.

Common Types

• Normally Open (NO): Circuit is open (off) until pushed.
• Normally Closed (NC): Circuit is closed (on) until pushed.
• Tactile Switch: Small, standard button for PCB mounting.

---

4. Switches (SW)

An electromechanical device that breaks or connects a circuit, staying in position until flipped.

Common Types

• SPST: Single Pole, Single Throw (On/Off)
• SPDT: Single Pole, Double Throw (Toggle between two paths)
• DPST/DPDT: Double Pole variants (controls two independent circuits simultaneously)
• DIP Switch: Small array of switches for circuit boards.

---

Quick Reference Summary Table

---

Common Suffixes

• k = kilo ($10^3$)
• M = Mega ($10^6$)
• m = milli ($10^{-3}$)
• µ = micro ($10^{-6}$)
• n = nano ($10^{-9}$)
• p = pico ($10^{-12}$)

Solderless Breadboard

A practical Markdown specification and reference for common solderless breadboards, intended for electronics prototyping, education, and hobbyist development.

---

1. Overview

A solderless breadboard is a reusable prototyping platform that allows electronic components to be interconnected without soldering. Connections are made via internal spring clips.

Typical Uses

• Rapid circuit prototyping
• Educational labs
• Logic and microcontroller experiments
• Low-power analog and digital circuits

Not Suitable For

• High current (>1A)
• High voltage (>36V)
• RF / high-frequency designs
• Vibration-prone or permanent installations

---

2. Physical Construction

Materials

• ABS or polystyrene body
• Phosphor bronze or nickel-plated spring contacts
• Adhesive backing (optional)

Standard Hole Pitch

• 2.54 mm (0.1 in) - compatible with DIP ICs and standard headers

Contact Characteristics

---

3. Internal Electrical Connections

Terminal Strips (Main Area)

• Rows of 5 interconnected holes
• Horizontal connectivity
• Center trench isolates left and right halves

A B C D E | F G H I J
──────────┼──────────
Connected | Connected

Power Rails

• Vertical buses on each side
• Often split in the middle (not always continuous)
• Usually marked red (+) and blue (-)

+  +  +  +  +   (may be split)
-  -  -  -  -

? Always verify continuity with a multimeter

---

4. Common Breadboard Sizes

---

5. Component Compatibility

Compatible Components

• DIP ICs (300 mil, 600 mil)
• Axial resistors and diodes
• LEDs
• Tactile switches
• Jumper wires
• Pin headers

Problematic Components

---

6. Electrical Characteristics

Typical Limits

Parasitics (Approximate)

---

7. Best Practices

Power Distribution

• Run ground and Vcc to both sides
• Bridge split power rails if needed
• Decouple ICs with 0.1µF ceramic capacitors

Wiring

• Keep wires short and tidy
• Use color coding:

• Red: Vcc
• Black/Blue: GND
• Yellow/White: Signals

IC Placement

• Place DIP ICs straddling the center trench
• Avoid forcing pins

---

8. Common Mistakes

---

9. Testing & Debugging

Continuity Check

• Verify rails and rows using a multimeter

Signal Integrity Tips

• Avoid breadboards for:

• High-speed clocks
• ADC precision circuits

---

10. Typical Breadboard Layout Example

[ + ] [ - ]   Power Rails
[ + ] [ - ]

 A B C D E | F G H I J
 A B C D E | F G H I J
 A B C D E | F G H I J

---

11. Accessories

---

12. Reference Links

• https://en.wikipedia.org/wiki/Breadboard
• https://learn.sparkfun.com/tutorials/how-to-use-a-breadboard
• https://www.allaboutcircuits.com/technical-articles/using-a-breadboard/

---

Document Scope: Solderless breadboard reference Audience: Hobbyist, student, engineer Status: Stable reference

Common Breadboard Electronic Components

A practical reference for breadboard-based electronics, covering common components, formulas, tables, pinouts, and learning references. Suitable for beginners through intermediate hardware builders.

---

1. Resistors

Description

Resistors limit current, divide voltage, and set bias points.

Common Types

Standard Values (E12 Series)

10, 12, 15, 18, 22, 27, 33, 39, 47, 56, 68, 82 x 10^n

Color Code

Power Ratings

Formulas

• Ohm's Law: V = I x R
• Power: P = V × I = I² × R = V² / R

Reference

• https://en.wikipedia.org/wiki/Resistor

---

2. Capacitors

Description

Capacitors store electrical energy and block DC while passing AC.

Common Types

Common Values

Voltage Rating Rule

Capacitor voltage rating ≥ 2x circuit voltage

Formulas

• Capacitive Reactance: Xc = 1 / (2πfC)
• Energy Stored: E = ½ C V²

Reference

• https://en.wikipedia.org/wiki/Capacitor

---

3. Inductors

Description

Inductors store energy in a magnetic field and resist changes in current.

Common Types

Formula

• Inductive Reactance: XL = 2πfL

Reference

• https://en.wikipedia.org/wiki/Inductor

---

4. Diodes

Description

Diodes allow current flow in one direction only.

Common Types

Key Parameters

Reference

• https://en.wikipedia.org/wiki/Diode

---

5. LEDs (Light Emitting Diodes)

Description

LEDs emit light when forward biased.

Typical Forward Voltage

Current Limiting Resistor

R = (V_supply - V_LED) / I_LED

Reference

• https://en.wikipedia.org/wiki/Light-emitting_diode

---

6. Transistors

BJT (Bipolar Junction Transistor)

Key Formula:

• Ic ≈ β × Ib

MOSFET

Reference

• https://en.wikipedia.org/wiki/Transistor

---

7. Integrated Circuits (DIP)

Common Logic Families

Decoupling Rule

Place 0.1µF ceramic capacitor across Vcc and GND per IC

Reference

• https://en.wikipedia.org/wiki/Integrated_circuit

---

8. Switches & Buttons

Debounce (RC Approximation)

• Typical: 10kΩ + 100nF

---

9. Breadboards

Description

Solderless prototyping boards with internal bus connections.

Internal Wiring

• Rows: connected horizontally (5 holes)
• Rails: connected vertically (power)

Limitations

• Not suitable for high-frequency or high-current circuits

Reference

• https://en.wikipedia.org/wiki/Breadboard

---

10. Common Accessories

---

11. Quick Reference Formulas

---

12. Learning Resources

• https://learn.sparkfun.com
• https://www.allaboutcircuits.com
• https://www.electronics-tutorials.ws
• https://en.wikipedia.org/wiki/Electronics

---

Document Purpose: Practical breadboard electronics reference Scope: Hobbyist, education, prototyping

Connecting Electronic Components

This guide provides step-by-step instructions for building electronic circuits on a breadboard. Each build progressively introduces new components and concepts.

---

Basic Component Build Instructions

Build 1 — Single LED

Components: Red LED, black jumper wire, red jumper wire, battery with holder

Steps:

1. Insert the black jumper wire into the breadboard from A5 to A14. 2. Insert the red jumper wire into the breadboard from J5 to J14. 3. Place the red LED into row 14 with the positive leg (the longer of the two legs) on the right side, aligned with the red wire, and the negative leg on the left, aligned with the black wire. 4. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.

Result: When you insert the battery, the LED will light up.

Troubleshooting:

• Is your LED inserted backwards?
• Are the jumper wires in the same row as the LED leads?
• Are the jumper wires in the same row as the battery terminals?

---

Build 2 — Single Push Button

Components: Red LED, push button, black jumper wire, red jumper wire, battery with holder

Steps:

1. Insert the black jumper wire into the breadboard from A5 to A16. 2. Insert the red jumper wire into the breadboard from J5 to J12. 3. Place the red LED into the breadboard with the positive leg (the longer of the two legs) inserted into H15 and the negative leg into G17. 4. Place the push button horizontally in the middle of the breadboard so the bottom-left pin is on row 16 (aligned with the black jumper wire) and the top-right pin is on row 14 (aligned with the negative leg of the red LED). 5. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.

Result: When you press the push button, the LED will light up.

Troubleshooting:

• Is your LED inserted backwards?
• Are the jumper wires in the same row as the LED leads?
• Are the jumper wires in the same row as the battery terminals?

---

Build 3 — Photoresistor-Dimmed LED

Components: Green LED, photoresistor, black jumper wire, red jumper wire, battery with holder

Steps:

1. Insert the black jumper wire into the breadboard from A5 to A12. 2. Insert the red jumper wire into the breadboard from J5 to J13. 3. Place the green LED into the breadboard with the positive leg (the longer of the two legs) inserted into F13 and the negative leg into E13. 4. Insert the photoresistor into the breadboard from C12 to D13. 5. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.

Result: When you insert the battery, the LED will light up. Covering the photoresistor will cause the LED to dim.

---

Build 4 — Double LED Push Button

Components: Red LED, green LED, 220Ω resistor, push button, black jumper wire, red jumper wire, battery with holder

Steps:

1. Insert the black jumper wire into the breadboard from A5 to A11. 2. Insert the red jumper wire into the breadboard from J5 to J11. 3. Insert the 220Ω resistor into the breadboard from I11 to I15. 4. Place the push button horizontally in the middle of the breadboard so the top pins are on row 15 and on opposite sides of the breadboard. 5. Place the red LED into the breadboard with the positive leg (the longer of the two legs) inserted into C17 and the negative leg into B11. 6. Place the green LED into the breadboard with the positive leg inserted into G15 and the negative leg into E11. 7. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.

Result: When you insert the battery, the green LED will light up. When you press the push button, the green LED will turn off and the red LED will light up.

Build 5 - Photoresistor Blinking LEDs

• Insert the black jumper wire into the breadboard from A3 to A12.
• Insert the red jumper wire into the breadboard from J3 to J12.
• Place the 555 integrated circuit chip into the middle of the breadboard with the top pins on row 12.
• Insert a jumper wire into the breadboard connecting D15 to G12.
• Insert a jumper wire into the breadboard connecting D13 to G14.
• Insert the 1000Ω resistor into the breadboard from C14 to H17.
• Insert the photoresistor into the breadboard from B14 to B15.
• Insert the capacitor into the breadboard from A13 to B12.
• Place the green LED into the breadboard with the positive leg (longer of the two legs) inserted into F17 and the negative leg into C12.
• Place the red LED into the breadboard with the positive leg inserted into I12 and the negative leg into J17.
• Insert the battery into its battery holder and place it in the breadboard, connecting negative to black and positive to red.

When you insert the battery, both LED’s will begin rapidly blinking. Covering the photoresistor from light will slow the LEDs blinking frequency.

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555 Timer IC Reference

The 555 timer is a versatile integrated circuit used in timing, pulse generation, and oscillator applications. The following sections provide pinout information and internal circuit details.

555 Pinout Diagram

    ┌─────────────────────────────────────┐
    │  ●                                  │
    │  #1                             #8  │
    │  ┌──┐                         ┌──┐  │
    │  │  │                         │  │  │
    │  └──┘                         └──┘  │
    │  #2                             #7  │
    │  ┌──┐       555 TIMER         ┌──┐  │
    │  │  │                         │  │  │
    │  └──┘                         └──┘  │
    │  #3                             #6  │
    │  ┌──┐                         ┌──┐  │
    │  │  │                         │  │  │
    │  └──┘                         └──┘  │
    │  #4                             #5  │
    │  ┌──┐                         ┌──┐  │
    │  │  │                         │  │  │
    │  └──┘                         └──┘  │
    └─────────────────────────────────────┘

555 Pin Descriptions

555 Internal Block Diagram

flowchart TB
    subgraph IC["555 Timer IC"]
        direction TB

        subgraph DIVIDER["Voltage Divider"]
            R1["R (5kΩ)"]
            R2["R (5kΩ)"]
            R3["R (5kΩ)"]
            R1 --- R2 --- R3
        end

        COMP1["Comparator 1<br/>(Threshold)"]
        COMP2["Comparator 2<br/>(Trigger)"]
        FF["Flip-Flop<br/>S-R"]
        OUT_STAGE["Output<br/>Stage"]
        DISCH_TR["Discharge<br/>Transistor"]
        VREF["Vref"]
    end

    PIN8["Pin 8<br/>Vcc"] --> R1
    R3 --> PIN1["Pin 1<br/>GND"]

    R1 -.->|"2/3 Vcc"| COMP1
    R2 -.->|"1/3 Vcc"| COMP2

    PIN6["Pin 6<br/>Threshold"] --> COMP1
    PIN2["Pin 2<br/>Trigger"] --> COMP2

    COMP1 -->|R| FF
    COMP2 -->|S| FF

    FF --> OUT_STAGE
    FF --> DISCH_TR

    OUT_STAGE --> PIN3["Pin 3<br/>Output"]
    DISCH_TR --> PIN7["Pin 7<br/>Discharge"]

    PIN4["Pin 4<br/>Reset"] --> FF
    PIN5["Pin 5<br/>Control Voltage"] -.-> R2

    style PIN1 fill:#000,color:#fff
    style PIN2 fill:#f96,color:#000
    style PIN3 fill:#6f6,color:#000
    style PIN4 fill:#f66,color:#000
    style PIN5 fill:#ff6,color:#000
    style PIN6 fill:#6ff,color:#000
    style PIN7 fill:#f6f,color:#000
    style PIN8 fill:#f00,color:#fff

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Build 6 — Push Button Buzzer

Components: 555 timer IC, piezo speaker, 220Ω resistor, 1000Ω resistor, capacitor, push button, jumper wires, battery with holder

Steps:

1. Insert the black jumper wire into the breadboard from A1 to A11. 2. Insert the red jumper wire into the breadboard from J1 to J11. 3. Place the 555 integrated circuit chip into the middle of the breadboard with the top pins on row 11. 4. Insert a jumper wire into the breadboard connecting D12 to G13. 5. Insert a jumper wire into the breadboard connecting D14 to G11. 6. Insert the capacitor into the breadboard from A12 to B11. 7. Insert the 220Ω resistor into the breadboard from C12 to C13. 8. Place the push button horizontally in the middle of the breadboard so the top pins are on row 15 and on opposite sides of the breadboard. 9. Insert the piezo speaker into the breadboard with the positive pin in A9 and the negative pin in A6. 10. Insert the 1000Ω resistor into the breadboard from E6 to A13. 11. Insert a jumper wire into the breadboard connecting C9 to D15. 12. Insert a jumper wire into the breadboard connecting G17 to I11. 13. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.

Result: When you press the push button, the buzzer will sound.

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Build 7 — Photoresistor Theremin

Components: 555 timer IC, piezo speaker, photoresistor, 1000Ω resistor, capacitor, push button, jumper wires, battery with holder

Steps:

1. Insert the black jumper wire into the breadboard from A1 to A11. 2. Insert the red jumper wire into the breadboard from J1 to J11. 3. Place the 555 integrated circuit chip into the middle of the breadboard with the top pins on row 11. 4. Insert a jumper wire into the breadboard connecting D12 to G13. 5. Insert a jumper wire into the breadboard connecting D14 to G11. 6. Insert the capacitor into the breadboard from A12 to B11. 7. Insert the photoresistor into the breadboard from C12 to C13. 8. Place the push button horizontally in the middle of the breadboard so the top pins are on row 15 and on opposite sides of the breadboard. 9. Insert the piezo speaker into the breadboard with the positive pin in A9 and the negative pin in A6. 10. Insert the 1000Ω resistor into the breadboard from E6 to A13. 11. Insert a jumper wire into the breadboard connecting C9 to D15. 12. Insert a jumper wire into the breadboard connecting G17 to I11. 13. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.

Result: When you press the push button, the buzzer will sound. Covering the photoresistor will change the pitch of the buzzer.

---

Build 8 — Potentiometer-Dimmed LED

Components: Green LED, potentiometer, 220Ω resistor, black jumper wire, red jumper wire, battery with holder

Steps:

1. Insert the black jumper wire into the breadboard from A1 to A13. 2. Insert the red jumper wire into the breadboard from J1 to J9. 3. Place the potentiometer with the two-pin side on the left, top pin in E13 and bottom pin in E15. 4. Insert the 220Ω resistor into the breadboard from H9 to H14. 5. Place the green LED into the breadboard with the positive leg (the longer of the two legs) inserted into C15 and the negative leg in B13. 6. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.

Result: When you insert the battery, the LED will turn on. Rotating the potentiometer will increase or decrease the brightness of the LED.

---

Build 9 — Push Button RGB LED

Components: RGB LED (common cathode), three push buttons, two 220Ω resistors, black jumper wire, red jumper wire, jumper wires, battery with holder

Steps:

1. Insert the black jumper wire into the breadboard from A1 to B7. 2. Insert the red jumper wire into the breadboard from J1 to J7. 3. Insert the RGB LED into the breadboard from A4 to A8. The longest of the four legs is the ground and should be in A7. 4. Place three push buttons horizontally in the middle of the breadboard with pins at:

• Button 1: E9–F9 and E11–F11
• Button 2: E12–F12 and E14–F14
• Button 3: E15–F15 and E17–F17

5. Insert a jumper wire into the breadboard connecting C5 to D9. 6. Insert a jumper wire into the breadboard connecting C6 to C12. 7. Insert a jumper wire into the breadboard connecting B8 to B15. 8. Insert the first 220Ω resistor into the breadboard from G7 to G11. 9. Insert the second 220Ω resistor into the breadboard from H7 to H14. 10. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.

Result: Pressing each push button will activate a different color channel of the RGB LED.

---

Build 10 — Potentiometer-Controlled Buzzer

Components: 555 timer IC, piezo speaker, potentiometer, 220Ω resistor, capacitor, push button, jumper wires, battery with holder

Steps:

1. Insert the black jumper wire into the breadboard from A1 to A11. 2. Insert the red jumper wire into the breadboard from J1 to J11. 3. Place the 555 integrated circuit chip into the middle of the breadboard with the top pins on row 11. 4. Insert a jumper wire into the breadboard connecting D12 to G13. 5. Insert a jumper wire into the breadboard connecting D14 to G11. 6. Insert the capacitor into the breadboard from A12 to B11. 7. Insert the piezo speaker into the breadboard from A6 to A9 (place the positive end on the bottom). 8. Place the push button horizontally in the middle of the breadboard so the top pins are in E15 and F15. 9. Insert the 220Ω resistor into the breadboard from E6 to A13. 10. Insert a jumper wire into the breadboard connecting E9 to D15. 11. Insert a jumper wire into the breadboard connecting G17 to I11. 12. Place the potentiometer with the two-pin side on the right, top pin in F7 and bottom pin in F9. 13. Insert a jumper wire into the breadboard connecting D8 to B13. 14. Insert a jumper wire into the breadboard connecting H7 to C12. 15. Insert a jumper wire into the breadboard connecting H9 to D11. 16. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.

Result: Pressing the push button will cause the buzzer to sound. Rotating the potentiometer will alter the pitch of the buzzer.

AT28C256 EEPROM Emulation Specification

Overview

This document specifies how to emulate the AT28C256 (32 KB Parallel EEPROM) in a 6502-based system emulator. The goal is behavioral accuracy suitable for SBCs, monitors, and real ROM images, not just generic file-backed storage.

The AT28C256 is commonly used as ROM in 6502 systems, but it is electrically writable and has timing behaviors that differ from SRAM.

---

Chip Summary

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Pin Definitions

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Read Cycle Behavior

A read occurs when:

/CE = 0
/OE = 0
/WE = 1

Read Rules

• Address must be stable before /OE is asserted
• Data appears on D0-D7 after access time (ignored in most emulators)
• Output is high-impedance when /OE = 1 or /CE = 1

Emulator Behavior

if CE == 0 and OE == 0 and WE == 1:
    data_bus = memory[address]
else:
    data_bus = Z

---

Write Cycle Behavior

A write occurs when:

/CE = 0
/WE = 0

(/OE is typically HIGH during writes)

Important EEPROM Characteristics

• Writes are not instantaneous
• Each write triggers an internal programming cycle
• During programming, reads may return undefined data

---

Write Timing Model (Simplified)

Real Hardware

Emulator Simplification Options

Option A - Instant Writes (Common)

• Write immediately updates memory
• No busy state
• Recommended for early emulators

Option B - Cycle-Based Busy State (Advanced)

• Track a "write in progress" timer
• Reads during write return last value or 0xFF
• Writes ignored until cycle completes

---

Page Write Emulation (Optional)

• Page size: 64 bytes
• Writes within same page before timeout commit together
• Crossing page boundary wraps within page (hardware quirk)

Simplified rule:

page_base = address & 0xFFC0
page_offset = address & 0x003F

---

Write Protection Behavior

Some systems treat EEPROM as ROM-only after programming.

Emulator may support:

• Read-only mode (writes ignored)
• Programmable mode (writes allowed)
• Runtime toggle (simulates programming jumper)

---

Power-Up State

• EEPROM retains contents
• No undefined data on power-up

Emulator should:

• Load contents from image file
• Preserve data across resets

---

Bus Contention Rules

Emulator may:

• Prioritize write
• Or flag invalid state

---

Memory Mapping in 6502 Systems

Common layout:

$0000-$7FFF  RAM
$8000-$FFFF  AT28C256 EEPROM

Reset Vector Usage

---

Emulator API Model

typedef struct {
    uint8_t memory[32768];
    bool write_enabled;
    bool busy;
    uint32_t busy_cycles;
} AT28C256;

Read

uint8_t eeprom_read(addr);

Write

void eeprom_write(addr, value);

---

Recommended Emulator Defaults

---

Testing Checklist

• Reset vector fetch
• ROM reads under normal execution
• Writes ignored in read-only mode
• Correct address masking (15 bits)
• No bus drive when disabled

---

References

• AT28C256 Datasheet (Microchip)
• Ben Eater 6502 Computer Series
• <https://www.youtube.com/watch?v=oO8_2JJV0B4>
• 6502.org Memory Mapping Notes

---

Notes

This specification intentionally mirrors real hardware quirks while allowing emulator authors to choose between simplicity and accuracy. It is suitable for:

• Educational emulators
• SBC simulation
• ROM development workflows
• Integration with 6502 + 6522 + SRAM emulation

AS6C62256 (32K x 8 SRAM) Emulation Specification

A technical Markdown specification for emulating the AS6C62256 / 62256-family static RAM, suitable for 6502-family emulators, SBC simulators, and memory subsystem modeling.

---

1. Scope

This document specifies functional behavior for emulating:

• Alliance Memory AS6C62256
• Compatible 62256 (32K x 8) SRAM devices

Out of scope:

• Analog electrical timing margins
• Bus contention and signal rise/fall times
• Power consumption characteristics

---

2. Chip Overview

Core Characteristics

---

3. External Signals (Logical Model)

# indicates active-low signals.

---

4. Address Space Mapping

• Address range: 0x0000-0x7FFF
• Address lines select one byte per address

Typical 6502 System Mapping Example

---

5. Read and Write Behavior

Read Cycle (Logical)

Conditions:

• CE# = 0
• OE# = 0
• WE# = 1

Behavior:

D[7:0]  memory[A]

If OE# = 1 or CE# = 1, data bus is high-impedance.

---

Write Cycle (Logical)

Conditions:

• CE# = 0
• WE# = 0

Behavior:

memory[A]  D[7:0]

• OE# is ignored during writes
• Write occurs on active WE#

---

6. Control Signal Priority

---

7. Emulator Interface Requirements

An emulator must expose:

read(address)  -> byte
write(address, byte)

Internal storage:

uint8_t ram[32768]

Address masking:

address = address & 0x7FFF

---

8. Timing Model (Abstracted)

Emulation Levels

For most systems, functional emulation is sufficient.

---

9. Power and Data Retention

• SRAM contents persist as long as power is applied
• Emulator shall retain contents until explicitly reset

Reset Behavior

• No automatic clearing on reset
• Memory contents undefined unless initialized

---

10. Bus Contention and Hi-Z Modeling (Optional)

Optional advanced behavior:

• Track when SRAM drives the data bus
• Detect illegal simultaneous writes

Most emulators may ignore Hi-Z state.

---

11. Error Conditions

---

12. Integration with 6502 Emulator

CPU memory access
  address decode
  if in SRAM range:
      AS6C62256.read/write

• SRAM access is typically single-cycle
• No wait states required

---

13. Testing and Validation

Basic Tests

• Write/read patterns
• Boundary addresses ($0000, $7FFF)
• Randomized memory tests

Validation Checklist

• Writes persist
• Reads return correct values
• Address wrapping correct

---

14. Common Mistakes

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15. Reference Links

• Alliance Memory AS6C62256 Datasheet
• https://en.wikipedia.org/wiki/Static_random-access_memory

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Document Scope: Software emulation of AS6C62256 SRAM Audience: Emulator developers, retro SBC designers Status: Stable technical reference